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[SYCL][CUDA] Move interop tests #1570

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76 changes: 4 additions & 72 deletions sycl/test/basic_tests/buffer/buffer.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,3 @@
// REQUIRES: opencl

// RUN: %clangxx %s -o %t1.out -lsycl -I %sycl_include
// RUN: env SYCL_DEVICE_TYPE=HOST %t1.out
// RUN: %clangxx -fsycl -fsycl-targets=%sycl_triple %s -o %t2.out
Expand All @@ -8,9 +6,6 @@
// RUN: %GPU_RUN_PLACEHOLDER %t2.out
// RUN: %ACC_RUN_PLACEHOLDER %t2.out

// TODO: Unexpected result and following assertion
// XFAIL: cuda

//==------------------- buffer.cpp - SYCL buffer basic test ----------------==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
Expand Down Expand Up @@ -397,8 +392,8 @@ int main() {

myQueue.submit([&](handler &cgh) {
accessor<int, 2, access::mode::write, access::target::global_buffer,
access::placeholder::false_t>
B(Buffer, cgh, range<2>(20,20), id<2>(10,10));
access::placeholder::false_t>
B(Buffer, cgh, range<2>(20, 20), id<2>(10, 10));
cgh.parallel_for<class bufferByRangeOffset>(
range<2>{10, 5}, [=](id<2> index) { B[index] = 1; });
});
Expand Down Expand Up @@ -494,9 +489,8 @@ int main() {
myQueue.submit([&](handler &cgh) {
auto B = b.get_access<access::mode::read_write>(cgh);
cgh.parallel_for<class wb>(range<1>{10},
[=](id<1> index) { B[index] = 0; });
[=](id<1> index) { B[index] = 0; });
});

}
// Data is copied back because there is a user side ptr and write-back is
// enabled
Expand All @@ -519,9 +513,8 @@ int main() {
myQueue.submit([&](handler &cgh) {
auto B = b.get_access<access::mode::read_write>(cgh);
cgh.parallel_for<class notwb>(range<1>{10},
[=](id<1> index) { B[index] = 0; });
[=](id<1> index) { B[index] = 0; });
});

}
// Data is not copied back because write-back is canceled
for (int i = 0; i < 10; i++)
Expand Down Expand Up @@ -551,33 +544,6 @@ int main() {
assert(data1[i] == 0);
}

{
queue myQueue;
if (!myQueue.is_host()) {
std::vector<int> data1(10, -1);
std::vector<int> data2(10, -2);
{
buffer<int, 1> a(data1.data(), range<1>(10));
buffer<int, 1> b(data2);

program prog(myQueue.get_context());
prog.build_with_source("kernel void override_source(global int* Acc) "
"{Acc[get_global_id(0)] = 0; }\n");
cl::sycl::kernel krn = prog.get_kernel("override_source");
myQueue.submit([&](handler &cgh) {
auto A = a.get_access<access::mode::read_write>(cgh);
cgh.set_arg(0, A);
auto B = b.get_access<access::mode::read_write>(cgh);
cgh.parallel_for(cl::sycl::range<1>(10), krn);
});
} // Data is copied back
for (int i = 0; i < 10; i++)
assert(data2[i] == -2);
for (int i = 0; i < 10; i++)
assert(data1[i] == 0);
}
}

{
std::vector<int> data1(10, -1);
std::vector<int> data2(10, -2);
Expand All @@ -604,40 +570,6 @@ int main() {
assert(data1[i] == 0);
}

{
queue myQueue;
if (!myQueue.is_host()) {
std::vector<int> data1(10, -1);
std::vector<int> data2(10, -2);
{
buffer<int, 1> a(data1.data(), range<1>(10));
buffer<int, 1> b(data2);
accessor<int, 1, access::mode::read_write,
access::target::global_buffer, access::placeholder::true_t>
A(a);
accessor<int, 1, access::mode::read_write,
access::target::global_buffer, access::placeholder::true_t>
B(b);

program prog(myQueue.get_context());
prog.build_with_source("kernel void override_source_placeholder(global "
"int* Acc) {Acc[get_global_id(0)] = 0; }\n");
cl::sycl::kernel krn = prog.get_kernel("override_source_placeholder");

myQueue.submit([&](handler &cgh) {
cgh.require(A);
cgh.set_arg(0, A);
cgh.require(B);
cgh.parallel_for(cl::sycl::range<1>(10), krn);
});
} // Data is copied back
for (int i = 0; i < 10; i++)
assert(data2[i] == -2);
for (int i = 0; i < 10; i++)
assert(data1[i] == 0);
}
}

{
int data[10];
void *voidPtr = (void *)data;
Expand Down
100 changes: 90 additions & 10 deletions sycl/test/basic_tests/buffer/buffer_interop.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
// RUN: %GPU_RUN_PLACEHOLDER %t.out
// RUN: %ACC_RUN_PLACEHOLDER %t.out

//==------------------- buffer.cpp - SYCL buffer basic test ----------------==//
//==------------------- buffer_interop.cpp - SYCL buffer basic test ---------==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
Expand Down Expand Up @@ -36,16 +36,16 @@ int main() {
buffer<int, 1> Buffer{OpenCLBuffer, MyQueue.get_context()};

if (Buffer.get_range() != InteropRange) {
assert(false);
Failed = true;
assert(false);
Failed = true;
}
if (Buffer.get_size() != InteropSize) {
assert(false);
Failed = true;
assert(false);
Failed = true;
}
if (Buffer.get_count() != Size) {
assert(false);
Failed = true;
assert(false);
Failed = true;
}

MyQueue.submit([&](handler &CGH) {
Expand All @@ -57,8 +57,7 @@ int main() {
int Data[Size] = {10};
std::vector<int> Result(Size, 0);
{
buffer<int, 1> BufferData{Data, range<1>{Size},
{property::buffer::use_host_ptr()}};
buffer<int, 1> BufferData{Data, range<1>{Size}, {property::buffer::use_host_ptr()}};
BufferData.set_final_data(Result.begin());
MyQueue.submit([&](handler &CGH) {
auto Data = BufferData.get_access<access::mode::write>(CGH);
Expand Down Expand Up @@ -132,7 +131,7 @@ int main() {
MyQueue.submit([&](handler &CGH) {
auto B = Buffer.get_access<access::mode::write>(CGH);
CGH.parallel_for<class HostAccess>(range<1>{Size},
[=](id<1> Index) { B[Index] = 10; });
[=](id<1> Index) { B[Index] = 10; });
});
auto Acc = Buffer.get_access<cl::sycl::access::mode::read>();
for (size_t i = 0; i < Size; ++i) {
Expand Down Expand Up @@ -183,5 +182,86 @@ int main() {
CHECK_OCL_CODE(clReleaseEvent(OpenCLEvent));
}

{
queue Queue;
if (!Queue.is_host()) {
std::vector<int> Data1(10, -1);
std::vector<int> Data2(10, -2);
{
buffer<int, 1> BufferA(Data1.data(), range<1>(10));
buffer<int, 1> BufferB(Data2);

program Program(Queue.get_context());
Program.build_with_source("kernel void override_source(global int* Acc) "
"{Acc[get_global_id(0)] = 0; }\n");
cl::sycl::kernel Kernel = Program.get_kernel("override_source");
Queue.submit([&](handler &CGH) {
auto AccA = BufferA.get_access<access::mode::read_write>(CGH);
CGH.set_arg(0, AccA);
auto AccB = BufferB.get_access<access::mode::read_write>(CGH);
CGH.parallel_for(cl::sycl::range<1>(10), Kernel);
});
} // Data is copied back
for (int i = 0; i < 10; i++) {
if (Data2[i] != -2) {
std::cout << " Data2[" << i << "] is " << Data2[i] << " expected " << -2 << std::endl;
assert(false);
Failed = true;
}
}
for (int i = 0; i < 10; i++) {
if (Data1[i] != 0) {
std::cout << " Data1[" << i << "] is " << Data1[i] << " expected " << 0 << std::endl;
assert(false);
Failed = true;
}
}
}
}

{
queue Queue;
if (!Queue.is_host()) {
std::vector<int> Data1(10, -1);
std::vector<int> Data2(10, -2);
{
buffer<int, 1> BufferA(Data1.data(), range<1>(10));
buffer<int, 1> BufferB(Data2);
accessor<int, 1, access::mode::read_write,
access::target::global_buffer, access::placeholder::true_t>
AccA(BufferA);
accessor<int, 1, access::mode::read_write,
access::target::global_buffer, access::placeholder::true_t>
AccB(BufferB);

program Program(Queue.get_context());
Program.build_with_source("kernel void override_source_placeholder(global "
"int* Acc) {Acc[get_global_id(0)] = 0; }\n");
cl::sycl::kernel Kernel = Program.get_kernel("override_source_placeholder");

Queue.submit([&](handler &CGH) {
CGH.require(AccA);
CGH.set_arg(0, AccA);
CGH.require(AccB);
CGH.parallel_for(cl::sycl::range<1>(10), Kernel);
});
} // Data is copied back
for (int i = 0; i < 10; i++) {
if (Data2[i] != -2) {
std::cout << " Data2[" << i << "] is " << Data2[i] << " expected " << -2 << std::endl;
assert(false);
Failed = true;
}
}
for (int i = 0; i < 10; i++) {
if (Data1[i] != 0) {
std::cout << " Data1[" << i << "] is " << Data1[i] << " expected " << 0 << std::endl;
assert(false);
Failed = true;
}
}
}
}

return Failed;
}