Low_Power_Multidimensional_Sorters

Low Power Multidimensional Sorters using Clock Gating and Index Sorting (Paper Link)

Published in: 2023 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)
DOI: 10.1109/CONECCT57959.2023.10234758

Maturity Level: Passed Gate Level Simulations with Positive Slack for 50MHz
Collateral: Verilog Design Files, SystemVerilog Layered TestBench, Constraints File

Library Used: Synopsys 90nm Typical VT (saed90nm_typ.lib)

Sorter Implementation	MDSA designs
Bitonic (24 CAE)	MDSA_bitonic MDSA_bitonic_index_merge MDSA_bitonic_index_pipeline
Hybrid (23 CAE)	MDSA_hybrid MDSA_hybrid_index
Odd Even (19 CAE)	MDSA_OE MDSA_OE_index

Testing Methodology: SystemVerilog Layered Testbench (for 100 iterations, using constraints and randomization for generating VCD)

• We further applied clock gating to all the above designs for further power reduction.

• Total 14 Implementations
  Lowest Power: MDSA Bitonic with Index and Clock Gating
  Lowest Area: MDSA Odd Even with Clock Gating

Licenses

Copyright (c) 2022 Samahith S A and Sai Govardhan

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Background of the project

BTech ECE Capstone Project (Team: N-08, Batch of ECE 2023) at PES University, Bangalore
Guide: Dr. Sudeendra Kumar K