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Achievements

Achievement: YOLOAchievement: Arctic Code Vault ContributorAchievement: Pull Shark

Achievements

Achievement: YOLOAchievement: Arctic Code Vault ContributorAchievement: Pull Shark

Highlights

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Organizations

@CIE-PESU

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govardhnn/README.adoc

Sai Govardhan

Hi, I’m a CPU uArch Design Engineer at InCore Semiconductors.

I graduated B.Tech in Electronics and Communication from PES University, with Teaching Assistant experience for three core subjects, eight Cadence Digital Badges for the Digital Design and Signoff track, and a VLSI Specialization. I have earlier worked at IIITB, IISC (OrbitAID), CIE PESU and CIOT PESU.

Digital Design

Computer Architecture

Scripting:

  • TCLish - a guide to TCL Scripting basics

My PES Student Teaching Assistant resources

(Please mail me at [email protected] for any doubts only if you’re a student from one of the below courses)

Other Projects

  • Built Farmbot, during my time interning at Centre for IOT, PESU.

Pinned Loading

  1. RISC_V_Single_Cycle_Processor RISC_V_Single_Cycle_Processor Public

    My implementation of the RISC-V Single Cycle Processor, based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition by Sarah Harris and David Harris

    Verilog 12 4

  2. DSD_AHP DSD_AHP Public

    A compilation of Cadence tool commands and AHP Projects(Specifications and Solutions) I provided as the Teaching Assistant for the Digital Systems Design course (UE20EC313) at PES University, Banga…

    Verilog 3

  3. RISC_V_Assembly_Programs RISC_V_Assembly_Programs Public

    A practice directory of RISC-V Assembly Programs

    Assembly

  4. UEFI_AHP UEFI_AHP Public

    My implementation of TianoCore's EDKII in QEMU as a part of my Student Teaching Assistant AHP Demo for the subject 'Embedded Firmware Development with UEFI'

  5. SPEC_CPU_2017 SPEC_CPU_2017 Public

    The SPEC CPU 2017 results for rate and speed, with instructions and custom interfacing methodology with Valgrind

    Shell 1 1

  6. CIE-PESU/DE10_FPGA CIE-PESU/DE10_FPGA Public

    Verilog