Regenerate on sdk-1.3.243.0 (#239)

* Regenerate on sdk-1.3.204.1 * Bump SPIR-V version in tests to `1.6` Our assembler uses the latest global version from the grammar (rather than encoding the highest `"version"` attribute of the instructions emitted). * Regenerate on sdk-1.3.211.0 * Regenerate on sdk-1.3.216.0 / sdk-1.3.224.1 * Tag sdk-1.3.216 points to the same commit as sdk-1.3.224.1 * Regenerate on sdk-1.3.231.1 * Regenerate on sdk-1.3.243.0 * Treat reserved `OpEmitMeshTasksEXT` as terminator * autogen: Reuse `dr` `is_terminator_instruction()` classification in `sr`
gfx-rs · Apr 8, 2023 · ba1f984 · ba1f984
1 parent aa260e0
commit ba1f984
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Showing 23 changed files with 7,166 additions and 1,674 deletions.
diff --git a/autogen/external/SPIRV-Headers b/autogen/external/SPIRV-Headers
diff --git a/autogen/src/dr.rs b/autogen/src/dr.rs
@@ -701,11 +701,11 @@ pub fn gen_dr_builder_types(grammar: &structs::Grammar) -> TokenStream {
     }
 }
 
-fn is_terminator_instruction(inst: &structs::Instruction) -> bool {
+pub fn is_terminator_instruction(inst: &structs::Instruction) -> bool {
     match inst.class {
         Some(structs::Class::Reserved) => matches!(
             inst.opname.as_str(),
-            "OpTerminateRayKHR" | "OpIgnoreIntersectionKHR"
+            "OpTerminateRayKHR" | "OpIgnoreIntersectionKHR" | "OpEmitMeshTasksEXT"
         ),
         Some(structs::Class::Branch) => !matches!(
             inst.opname.as_str(),

diff --git a/autogen/src/sr.rs b/autogen/src/sr.rs
@@ -447,7 +447,7 @@ pub fn gen_sr_code_from_instruction_grammar(
                     });
                 }
             }
-            Some(Reserved) if matches!(inst_name, "TerminateRayKHR" | "IgnoreIntersectionKHR") => {
+            Some(Reserved) if super::dr::is_terminator_instruction(inst) => {
                 if field_names.is_empty() {
                     terminator_variants.push(quote! { #name_ident });
                     terminator_lifts.push(quote! {
@@ -536,6 +536,7 @@ pub fn gen_sr_code_from_instruction_grammar(
             pub fn lift_terminator(
                 &mut self, raw: &dr::Instruction
             ) -> Result<ops::Terminator, InstructionError> {
+                let mut #iter_ident = raw.operands.iter();
                 match raw.class.opcode as u32 {
                     #( #terminator_lifts )*
                     _ => self.lift_branch(raw)

diff --git a/rspirv/Cargo.toml b/rspirv/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "rspirv"
-version = "0.11.0+sdk-1.2.198"
+version = "0.11.0+sdk-1.3.243.0"
 authors = ["Lei Zhang <[email protected]>"]
 edition = "2018"
 

diff --git a/rspirv/README.md b/rspirv/README.md
@@ -34,7 +34,7 @@ First add to your `Cargo.toml`:
 
 ```toml
 [dependencies]
-rspirv = "0.11.0+sdk-1.2.198"
+rspirv = "0.11.0"
 ```
 
 Examples

diff --git a/rspirv/binary/autogen_disas_operand.rs b/rspirv/binary/autogen_disas_operand.rs
@@ -62,6 +62,9 @@ impl Disassemble for spirv::ImageOperands {
         if self.contains(spirv::ImageOperands::ZERO_EXTEND) {
             bits.push("ZeroExtend")
         }
+        if self.contains(spirv::ImageOperands::NONTEMPORAL) {
+            bits.push("Nontemporal")
+        }
         if self.contains(spirv::ImageOperands::OFFSETS) {
             bits.push("Offsets")
         }
@@ -170,6 +173,12 @@ impl Disassemble for spirv::LoopControl {
         if self.contains(spirv::LoopControl::NO_FUSION_INTEL) {
             bits.push("NoFusionINTEL")
         }
+        if self.contains(spirv::LoopControl::LOOP_COUNT_INTEL) {
+            bits.push("LoopCountINTEL")
+        }
+        if self.contains(spirv::LoopControl::MAX_REINVOCATION_DELAY_INTEL) {
+            bits.push("MaxReinvocationDelayINTEL")
+        }
         bits.join("|")
     }
 }
@@ -290,6 +299,12 @@ impl Disassemble for spirv::MemoryAccess {
         if self.contains(spirv::MemoryAccess::NON_PRIVATE_POINTER_KHR) {
             bits.push("NonPrivatePointerKHR")
         }
+        if self.contains(spirv::MemoryAccess::ALIAS_SCOPE_INTEL_MASK) {
+            bits.push("AliasScopeINTELMask")
+        }
+        if self.contains(spirv::MemoryAccess::NO_ALIAS_INTEL_MASK) {
+            bits.push("NoAliasINTELMask")
+        }
         bits.join("|")
     }
 }
@@ -341,6 +356,9 @@ impl Disassemble for spirv::RayFlags {
         if self.contains(spirv::RayFlags::SKIP_AAB_BS_KHR) {
             bits.push("SkipAABBsKHR")
         }
+        if self.contains(spirv::RayFlags::FORCE_OPACITY_MICROMAP2_STATE_EXT) {
+            bits.push("ForceOpacityMicromap2StateEXT")
+        }
         bits.join("|")
     }
 }

diff --git a/rspirv/binary/autogen_parse_operand.rs b/rspirv/binary/autogen_parse_operand.rs
@@ -236,7 +236,10 @@ impl<'c, 'd> Parser<'c, 'd> {
         if loop_control.contains(spirv::LoopControl::SPECULATED_ITERATIONS_INTEL) {
             params.append(&mut vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]);
         }
-        if loop_control.contains(spirv::LoopControl::NO_FUSION_INTEL) {
+        if loop_control.contains(spirv::LoopControl::LOOP_COUNT_INTEL) {
+            params.append(&mut vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]);
+        }
+        if loop_control.contains(spirv::LoopControl::MAX_REINVOCATION_DELAY_INTEL) {
             params.append(&mut vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]);
         }
         Ok(params)
@@ -255,6 +258,12 @@ impl<'c, 'd> Parser<'c, 'd> {
         if memory_access.contains(spirv::MemoryAccess::MAKE_POINTER_VISIBLE) {
             params.append(&mut vec![dr::Operand::IdScope(self.decoder.id()?)]);
         }
+        if memory_access.contains(spirv::MemoryAccess::ALIAS_SCOPE_INTEL_MASK) {
+            params.append(&mut vec![dr::Operand::IdRef(self.decoder.id()?)]);
+        }
+        if memory_access.contains(spirv::MemoryAccess::NO_ALIAS_INTEL_MASK) {
+            params.append(&mut vec![dr::Operand::IdRef(self.decoder.id()?)]);
+        }
         Ok(params)
     }
     #[allow(unreachable_patterns)]
@@ -348,6 +357,15 @@ impl<'c, 'd> Parser<'c, 'd> {
             spirv::ExecutionMode::SchedulerTargetFmaxMhzINTEL => {
                 vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
             }
+            spirv::ExecutionMode::StreamingInterfaceINTEL => {
+                vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+            }
+            spirv::ExecutionMode::RegisterMapInterfaceINTEL => {
+                vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+            }
+            spirv::ExecutionMode::NamedBarrierCountINTEL => {
+                vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+            }
             _ => vec![],
         })
     }
@@ -460,6 +478,21 @@ impl<'c, 'd> Parser<'c, 'd> {
             spirv::Decoration::PrefetchINTEL => {
                 vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
             }
+            spirv::Decoration::MathOpDSPModeINTEL => vec![
+                dr::Operand::LiteralBit32(self.decoder.bit32()?),
+                dr::Operand::LiteralBit32(self.decoder.bit32()?),
+            ],
+            spirv::Decoration::AliasScopeINTEL => vec![dr::Operand::IdRef(self.decoder.id()?)],
+            spirv::Decoration::NoAliasINTEL => vec![dr::Operand::IdRef(self.decoder.id()?)],
+            spirv::Decoration::InitiationIntervalINTEL => {
+                vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+            }
+            spirv::Decoration::MaxConcurrencyINTEL => {
+                vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+            }
+            spirv::Decoration::PipelineEnableINTEL => {
+                vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+            }
             spirv::Decoration::BufferLocationINTEL => {
                 vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
             }
@@ -470,6 +503,34 @@ impl<'c, 'd> Parser<'c, 'd> {
                 dr::Operand::LiteralBit32(self.decoder.bit32()?),
                 dr::Operand::FPOperationMode(self.decoder.fp_operation_mode()?),
             ],
+            spirv::Decoration::LatencyControlLabelINTEL => {
+                vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+            }
+            spirv::Decoration::LatencyControlConstraintINTEL => vec![
+                dr::Operand::LiteralBit32(self.decoder.bit32()?),
+                dr::Operand::LiteralBit32(self.decoder.bit32()?),
+                dr::Operand::LiteralBit32(self.decoder.bit32()?),
+            ],
+            spirv::Decoration::MMHostInterfaceAddressWidthINTEL => {
+                vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+            }
+            spirv::Decoration::MMHostInterfaceDataWidthINTEL => {
+                vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+            }
+            spirv::Decoration::MMHostInterfaceLatencyINTEL => {
+                vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+            }
+            spirv::Decoration::MMHostInterfaceReadWriteModeINTEL => {
+                vec![dr::Operand::AccessQualifier(
+                    self.decoder.access_qualifier()?,
+                )]
+            }
+            spirv::Decoration::MMHostInterfaceMaxBurstINTEL => {
+                vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+            }
+            spirv::Decoration::MMHostInterfaceWaitRequestINTEL => {
+                vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
+            }
             _ => vec![],
         })
     }

diff --git a/rspirv/binary/disassemble.rs b/rspirv/binary/disassemble.rs
@@ -334,7 +334,7 @@ mod tests {
         assert_eq!(
             b.module().disassemble(),
             "; SPIR-V\n\
-                    ; Version: 1.5\n\
+                    ; Version: 1.6\n\
                     ; Generator: rspirv\n\
                     ; Bound: 8\n\
                     OpCapability Shader\n\
@@ -403,7 +403,7 @@ mod tests {
         assert_eq!(
             b.module().disassemble(),
             "; SPIR-V\n\
-                    ; Version: 1.5\n\
+                    ; Version: 1.6\n\
                     ; Generator: rspirv\n\
                     ; Bound: 18\n\
                     OpCapability Shader\n\
@@ -458,7 +458,7 @@ mod tests {
         assert_eq!(
             b.module().disassemble(),
             "; SPIR-V\n\
-                    ; Version: 1.5\n\
+                    ; Version: 1.6\n\
                     ; Generator: rspirv\n\
                     ; Bound: 9\n\
                     OpCapability Shader\n\
@@ -502,7 +502,7 @@ mod tests {
         assert_eq!(
             b.module().disassemble(),
             "; SPIR-V\n\
-                    ; Version: 1.5\n\
+                    ; Version: 1.6\n\
                     ; Generator: rspirv\n\
                     ; Bound: 9\n\
                     %1 = OpExtInstImport \"OpenCL.std\"\n\
+9 −5		CMakeLists.txt
+14 −8		include/spirv/spir-v.xml
+23 −1		include/spirv/unified1/NonSemanticClspvReflection.h
+50 −0		include/spirv/unified1/NonSemanticDebugBreak.h
+174 −2		include/spirv/unified1/extinst.nonsemantic.clspvreflection.grammar.json
+9 −0		include/spirv/unified1/extinst.nonsemantic.debugbreak.grammar.json
+1,984 −0		include/spirv/unified1/spirv.bf
+1,503 −65		include/spirv/unified1/spirv.core.grammar.json
+160 −3		include/spirv/unified1/spirv.cs
+227 −12		include/spirv/unified1/spirv.h
+258 −13		include/spirv/unified1/spirv.hpp
+258 −13		include/spirv/unified1/spirv.hpp11
+165 −14		include/spirv/unified1/spirv.json
+160 −3		include/spirv/unified1/spirv.lua
+160 −3		include/spirv/unified1/spirv.py
+160 −3		include/spirv/unified1/spv.d
+1 −0		tools/buildHeaders/bin/makeExtinstHeaders.py
+61 −8		tools/buildHeaders/header.cpp
+1 −0		tools/buildHeaders/header.h
+3 −0		tools/buildHeaders/main.cpp