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Accept import between module name and parameter/port list #137

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fabianschuiki opened this issue May 2, 2020 · 0 comments
Closed

Accept import between module name and parameter/port list #137

fabianschuiki opened this issue May 2, 2020 · 0 comments
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A-parser Area: Parser. C-bug Category: This is a bug. L-vlog Language: Verilog and SystemVerilog.

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@fabianschuiki
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Currently does not parse:

module foo1 import magic::*;;
endmodule
@fabianschuiki fabianschuiki added C-bug Category: This is a bug. L-vlog Language: Verilog and SystemVerilog. A-parser Area: Parser. labels May 2, 2020
@fabianschuiki fabianschuiki mentioned this issue May 2, 2020
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fabianschuiki added a commit that referenced this issue May 2, 2020
@fabianschuiki
test: Add cases for common_cells issues
7f66756 
See #137, #138, #139, and #140.
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A-parser Area: Parser. C-bug Category: This is a bug. L-vlog Language: Verilog and SystemVerilog.
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