add ifdef peripheral included #288

davideschiavone · 2023-05-26T06:11:14Z

No description provided.

JoseCalero

let's avoid even the possibility to compile those

JoseCalero · 2023-05-26T08:09:55Z

sw/applications/example_external_peripheral/main.c

@@ -25,6 +25,10 @@ plic_irq_id_t intr_num;
 int main(int argc, char *argv[])
 {

+#ifndef RV_PLIC_IS_INCLUDED
+  #pragma message ( "This app does NOT work as the RV_PLIC peripheral is not included" )


I would output an error, so the app is not even compiled. If we do not have the PLIC for example, why do we want the app to be able to be compiled? so:
#pragma error ( "This app does NOT work as the RV_PLIC peripheral is not included" )
or
#error ( "This app does NOT work as the RV_PLIC peripheral is not included" )
Both work

We have to be careful with this or the CI might reject every push. We might need to compile for both targets and make a logic OR maybe?

yes I kept it like this as otherwise the application does not end, maybe it is better to return 0 rather than -1 as indeed the CI may complain that application which is not supposed to run fail

Having talked with Jose we agree that an error would be a good solution.

and what about the CI?

so, we want the application to be able to run even though we do not have (for example) the PLIC included?

no but the CI compiles anyway all the program and a future CI task may run all the applications, so we need to find a way that the CI does not report "errors" -

But if I push an application that requires a change in the mcu_cfg.hjson to compile, I think the CI should raise an error.

unless i am missing something, I agree

done @JuanSapriza @JoseCalero

davideschiavone · 2023-05-30T06:42:36Z

the CI fails as discussed above, the PDM2PCM peripheral is not included, hence the error when trying to compile it - either we do not compile them all, or another solution is needed

JuanSapriza · 2023-05-30T06:48:30Z

the CI fails as discussed above, the PDM2PCM peripheral is not included, hence the error when trying to compile it - either we do not compile them all, or another solution is needed

I guess that the pcd2pcm is not included because a) it is not ready yet, or b) It a feature specific to a particular domain.

If the case is a), I understand it should have its own branch, and not be pushed to main.
If the case is b), maybe we should include it and add a step in the configuration of the project suggesting to go and disable whatever is not needed.

davideschiavone · 2023-05-30T07:02:13Z

the CI fails as discussed above, the PDM2PCM peripheral is not included, hence the error when trying to compile it - either we do not compile them all, or another solution is needed

I guess that the pcd2pcm is not included because a) it is not ready yet, or b) It a feature specific to a particular domain.

If the case is a), I understand it should have its own branch, and not be pushed to main. If the case is b), maybe we should include it and add a step in the configuration of the project suggesting to go and disable whatever is not needed.

x-heep is configurable, so it allows to have or not a given peripheral by modifying the mcu-gen - so by default, the pdm2pcm is not included (for whatever reason) so being in the main branch is a must, so we need to find another solution

JuanSapriza · 2023-05-30T08:55:38Z

(Thinking out loud). One thing we could have is some sort of configuration/requirements-file per app. Before compiling we could check that file, compare to what is already generated and, if there is a difference, make mcu-gen with the proper configuration.

We might need to change a few things, because we would need the mcu-gen (or maybe some other script) to modify mcu-cfg.

I think that excluding some apps from the CI is a very risky alternative (it reduces the usefulness of having the CI in the first place).

JoseCalero · 2023-05-30T08:59:29Z

the CI fails as discussed above, the PDM2PCM peripheral is not included, hence the error when trying to compile it - either we do not compile them all, or another solution is needed

I guess that the pcd2pcm is not included because a) it is not ready yet, or b) It a feature specific to a particular domain.
If the case is a), I understand it should have its own branch, and not be pushed to main. If the case is b), maybe we should include it and add a step in the configuration of the project suggesting to go and disable whatever is not needed.

x-heep is configurable, so it allows to have or not a given peripheral by modifying the mcu-gen - so by default, the pdm2pcm is not included (for whatever reason) so being in the main branch is a must, so we need to find another solution

Given that the PDM2PCM peripheral still needs some work I would come back then for the warnings implementations, just as a temporary solution (although the warning is gonna be 'lost' in the looong output of the CI). To avoid this type of problem in the future, there are different options/possibilities:

avoid merging peripherals/apps (whatever) that do not work/haven't been tested properly. (As the project gets bigger, this is gonna be challenging)
X-HEEP is configurable (e.g.: yes/no included peripherals), but if by default (main branch) we do not include a peripheral, maybe its application should be placed in another folder? (CI is gonna compile just the ones that are under the applications folder).
forget about 1 and 2, and just add warnings.

what do you think?

davideschiavone · 2023-05-30T09:20:10Z

the CI fails as discussed above, the PDM2PCM peripheral is not included, hence the error when trying to compile it - either we do not compile them all, or another solution is needed

I guess that the pcd2pcm is not included because a) it is not ready yet, or b) It a feature specific to a particular domain.
If the case is a), I understand it should have its own branch, and not be pushed to main. If the case is b), maybe we should include it and add a step in the configuration of the project suggesting to go and disable whatever is not needed.

x-heep is configurable, so it allows to have or not a given peripheral by modifying the mcu-gen - so by default, the pdm2pcm is not included (for whatever reason) so being in the main branch is a must, so we need to find another solution

Given that the PDM2PCM peripheral still needs some work I would come back then for the warnings implementations, just as a temporary solution (although the warning is gonna be 'lost' in the looong output of the CI). To avoid this type of problem in the future, there are different options/possibilities:

avoid merging peripherals/apps (whatever) that do not work/haven't been tested properly. (As the project gets bigger, this is gonna be challenging)

X-HEEP is configurable (e.g.: yes/no included peripherals), but if by default (main branch) we do not include a peripheral, maybe its application should be placed in another folder? (CI is gonna compile just the ones that are under the applications folder).

forget about 1 and 2, and just add warnings.

what do you think?

The test for the pdm2pcm peripheral works, it is just that the peripheral it is not included by default - so it can even be that another peripheral (say spi2) gets excluded for area reason, then we could come back to this problem anyway for apps that use the spi2
I do not like tbh
the error is ok - I think we should just have a CI_list.txt instead of compiling all the possible applications - this CI_list.txt should be carefully updated and maintained of course, but at least we check only what we want

JuanSapriza · 2023-05-30T10:53:10Z

3. the error is ok - I think we should just have a CI_list.txt instead of compiling all the possible applications - this CI_list.txt should be carefully updated and maintained of course, but at least we check only what we want

What I dont like about this is that we will not be testing this app in the CI. If some change brakes it, we might not find out.

davideschiavone · 2023-05-30T11:07:19Z

3. the error is ok - I think we should just have a CI_list.txt instead of compiling all the possible applications - this CI_list.txt should be carefully updated and maintained of course, but at least we check only what we want
What I dont like about this is that we will not be testing this app in the CI. If some change brakes it, we might not find out.

yes but I do not have an alternative - do you?

JuanSapriza · 2023-05-30T12:21:29Z

(Thinking out loud). One thing we could have is some sort of configuration/requirements-file per app. Before compiling we could check that file, compare to what is already generated and, if there is a difference, make mcu-gen with the proper configuration.

@davideschiavone Do you think this would be too much work? I think it would be the better option in the mid-term

davideschiavone · 2023-05-30T13:01:36Z

(Thinking out loud). One thing we could have is some sort of configuration/requirements-file per app. Before compiling we could check that file, compare to what is already generated and, if there is a difference, make mcu-gen with the proper configuration.

@davideschiavone Do you think this would be too much work? I think it would be the better option in the mid-term

It is easier if we enable all the peripherals by default and let others enable/disable them passing a different mcu.hjson file - which could also make sense to me (as we already did with the PADs) - shall we do this way?

The issue I see are:

1 - when we will have many peripherals, the FPGA will complain about the size, and thus we need to maintain 2 mcu_cfg.hson file (100% source of error)

2 - people interested in having a small x-heep version (which is the main target) will have to modify manually the mcu hjson file again - this may prevent usage or making the access barrier higher

JuanSapriza · 2023-05-30T13:55:20Z

Could we add a parameter in the mcu-gen that determines which mcu-cfg to use? (mcu_cfg_full.hjson or mcu_cfg_light.hjson). By default we can grab the light one, but in the CI we can override this and always compile with the full version. This way, for the average user its transparent.

Furthermore, the full version could use the light one as base and just add some more components (as a form of patch)? (I might be delusional here)

davideschiavone · 2023-05-30T18:03:00Z

Could we add a parameter in the mcu-gen that determines which mcu-cfg to use? (mcu_cfg_full.hjson or mcu_cfg_light.hjson). By default we can grab the light one, but in the CI we can override this and always compile with the full version. This way, for the average user its transparent.

Furthermore, the full version could use the light one as base and just add some more components (as a form of patch)? (I might be delusional here)

actually it is a good idea, but of I may, I would do an mcu_cfg_ci and and mcu_cfg. What do you think ?

or even better, locally modifying mcu cfg (with SED, replacing is included no with is included yes)

JuanSapriza · 2023-05-31T06:33:24Z

Indeed that's the easiest solution!
The CI could be updated as:

sed 's/is_included: "no",/is_included: "yes",/' -i mcu_cfg.hjson
make mcu-gen

I tested this change in this PR by reverting the changes of the CI_list.txt and it works.

I made PR #293. Once merged this PR needs to revert those changes as well and then can be merged.

JoseCalero · 2023-05-31T09:22:32Z

Indeed that's the easiest solution! The CI could be updated as:
sed 's/is_included: "no",/is_included: "yes",/' -i mcu_cfg.hjson
make mcu-gen
I tested this change in this PR by reverting the changes of the CI_list.txt and it works.

I made PR #293. Once merged this PR needs to revert those changes as well and then can be merged.

#293 was merged.

davideschiavone · 2023-05-31T10:54:07Z

Indeed that's the easiest solution! The CI could be updated as:
sed 's/is_included: "no",/is_included: "yes",/' -i mcu_cfg.hjson
make mcu-gen
I tested this change in this PR by reverting the changes of the CI_list.txt and it works.
I made PR #293. Once merged this PR needs to revert those changes as well and then can be merged.
#293 was merged.

Merged back in this branch - I would say it is ready to be merged @JoseCalero @JuanSapriza

Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 435c869a6861f71a045d91464cdedbcf6d1777e7 * Interrupt ID to the intr handlers of the PLIC (esl-epfl/x-heep#315) (JuanSapriza) * add ports to DMA to write to addresses coming from port2 of DMA (esl-epfl/x-heep#320) (Davide Schiavone) * DMA HAL - clean PR (esl-epfl/x-heep#317) (JuanSapriza) * Cleaning up flags (esl-epfl/x-heep#316) (Davide Schiavone) * Add support for externally defined external pads in `Makefile` (esl- epfl/x-heep#312) (Michele Caon) * Linker load flash refactor fill memory (esl-epfl/x-heep#294) (jmiranda) * add i2s peripheral (esl-epfl/x-heep#203) (Tim Frey) * Add example ADC schematic (esl-epfl/x-heep#309) (Cyril) * Update `cv32e40x` version to `0.9.0` (esl-epfl/x-heep#308) (Michele Caon) * integration of an AMS peripheral example (esl-epfl/x-heep#270) (Cyril) * Update FuseSoC remote (esl-epfl/x-heep#307) (Michele Caon) * fix USE_SPI_FLASH for FPGA (esl-epfl/x-heep#301) (Davide Schiavone) * add ifdef peripheral included (esl-epfl/x-heep#288) (Davide Schiavone) * Added command in CI to include all peripherals before building. (esl-epfl/x-heep#293) (JuanSapriza) Signed-off-by: Juan Sapriza <[email protected]>

* Updated README file to refer to x-heep repo documentation. * Corrected a typo * Made the link specific to prequisite section * Modified vendor hjson * Update esl_epfl_x_heep to esl-epfl/x-heep@495ad7a Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 495ad7ac19c2bfd6a0cc8c68deafccdfb2f7da3b * update docs (esl-epfl/x-heep#209) (David Mallasén Quintana) * Automatisation of CMake back-end (esl-epfl/x-heep#207) (jmiranda) * Add initial guide on extending X-HEEP with CORE-V-XIF (esl- epfl/x-heep#205) (David Mallasén Quintana) * update app (davide schiavone) * update debug.md (Davide Schiavone) * add FreeRTOS support and CMake compatible sw compilation (esl- epfl/x-heep#191) (jmiranda) * add support for cv32e40x (esl-epfl/x-heep#197) (David Mallasén Quintana) * fix common cell (davide schiavone) * [wip] add support for SkyWater130 and OpenRoad (esl-epfl/x-heep#181) (Davide Schiavone) * add Linux-hosted fpga emulation platform (femu) (esl- epfl/x-heep#189) (Saverio Nasturzio) * fix stepi on cve2 (Schiavone Pasquale Davide) * automatic structs generation (esl-epfl/x-heep#196) (Stefano Albini) * automate peripheral integration (esl-epfl/x-heep#195) (fimtrey) * new gpio from pulp (esl-epfl/x-heep#186) (Davide Schiavone) * clock-gating of peripheral subsystem and memory banks (esl- epfl/x-heep#187) (Saverio Nasturzio) * Auto create virtualenv for FuseSoC + other python scripts (esl- epfl/x-heep#188) (Manuel Eggimann) * fix apps and linker script (esl-epfl/x-heep#176) (Simone Machetti) * add spi2 in peripheral domain (esl-epfl/x-heep#180) (Davide Schiavone) * Fixed error in block diagram. (esl-epfl/x-heep#178) (Simone Machetti) * Update README.md (Davide Schiavone) * Added block diagrams. (esl-epfl/x-heep#177) (Simone Machetti) * Update README.md (Davide Schiavone) Signed-off-by: Juan Sapriza <[email protected]> * Modified internal sw structure * Modified folder structure to be compatible with the new compilation flow * renamed the x-heep vendor files * Update esl_epfl_x_heep to esl-epfl/x-heep@c87d7ea Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision c87d7ea9888a4353177b76b790019cf1c0c2c481 * add sw build from external (esl-epfl/x-heep#217) (JuanSapriza) * Update OpenTitan doc links in README.md (esl-epfl/x-heep#216) (ruben-roalvarez) * Removed bit-fields from peripherlas' structs generation (esl- epfl/x-heep#213) (Stefano Albini) * fix esl-epfl/x-heep#71 (Davide Schiavone) * Automate interrupt integration (esl-epfl/x-heep#202) (fimtrey) * Add LLVM-Clang support (esl-epfl/x-heep#208) (David Mallasén Quintana) * Update OpenRoadFlow.md (Davide Schiavone) * Fix questasim simulation with flash (esl-epfl/x-heep#211) (David Mallasén Quintana) Signed-off-by: Juan Sapriza <[email protected]> * Added vendor file (was not untracked before). * Major changes to make the cgra code compile * Made the necessary changes for verilator-sim to work * Updated a name in func_test main.c * It is possible to simulate a test from uppermost source folder, with cgra, via make run PROJECT=cgra_dbl_search * Compiles both CGRA apps, now includes .c files in the project folder * Made changes in Compilation flow to include files from linked folders. * Reduced the CMakeLists to make it more scalable. * Cleaned up the CMakelists a bit * Added / around the folder criteria to add files to list to prevent files with keywords in the name from being added. * Updated the CMakelist to match changes done in x-heep branch (not yet merged, but to prevent missing this by mistake) * Updated the vendor file to include a specific SHA * Update esl_epfl_x_heep to esl-epfl/x-heep@95256ea Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 95256ea6f01b665222be18c05ead2da1303729b8 * add tc_clk_xor2 (esl-epfl/x-heep#225) (Tim Frey) * fix venv / conda envs (esl-epfl/x-heep#221) (Davide Schiavone) * update common cells (esl-epfl/x-heep#223) (Davide Schiavone) * Add pynq-z2 board files (esl-epfl/x-heep#212) (David Mallasén Quintana) * Fixed two bugs (OBJ_PATH for clang and creeation of links). (esl- epfl/x-heep#222) (JuanSapriza) * add sw build from external (esl-epfl/x-heep#217) (JuanSapriza) * Update OpenTitan doc links in README.md (esl-epfl/x-heep#216) (ruben-roalvarez) * Removed bit-fields from peripherlas' structs generation (esl- epfl/x-heep#213) (Stefano Albini) * fix esl-epfl/x-heep#71 (Davide Schiavone) * Automate interrupt integration (esl-epfl/x-heep#202) (fimtrey) * Add LLVM-Clang support (esl-epfl/x-heep#208) (David Mallasén Quintana) * Update OpenRoadFlow.md (Davide Schiavone) * Fix questasim simulation with flash (esl-epfl/x-heep#211) (David Mallasén Quintana) Signed-off-by: Juan Sapriza <[email protected]> * updated the README to point to the vendorized documentation. * Updated vendor file to add fpga board files * Update esl_epfl_x_heep to esl-epfl/x-heep@158a70c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 158a70c92b16a7ab207fe25eae6e131e461d631d * Add pynq-z2 board files (esl-epfl/x-heep#212) (David Mallasén Quintana) * Fixed two bugs (OBJ_PATH for clang and creeation of links). (esl- epfl/x-heep#222) (JuanSapriza) Signed-off-by: Juan Sapriza <[email protected]> * In this configuration it is possible to make vivado-fpga. CGRA working on FPGA * Cleaned the files modified for the synthesis for fpga * Restored the CGRA files to they original values and added external cgra_fpga files. Synthezised and tested on FPGA * Removed some changes done inside the cgra * Fixed some names that were modified in previous commits. * Removed visibility signals where they didnt belong so it could be built for simulation * Removed unnecessary signals * Added some commands to quickly load into the fpga * Updated CMakeLists.txt file from x-heep to allow seemless building of apps in the x-heep repo * Added the License file * Renamed vendor files for consistency with lint checks * Updated the vendor sha * Update esl_epfl_x_heep to esl-epfl/x-heep@9eb9c1c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 9eb9c1c61fc4cbd0502d58f3dc1c43e07f1f7018 * Add LICENSE (davide schiavone) * Add F-HEEP to the eXtendingHEEP list (esl-epfl/x-heep#257) (David Mallasén Quintana) * add fast interrupt enable register (esl-epfl/x-heep#256) (Tim Frey) * improved interrupt integration (esl-epfl/x-heep#255) (Tim Frey) * Peripherals structs _reserved fields renaming (esl-epfl/x-heep#254) (Stefano Albini) * adding bitfield_read/write functions (esl-epfl/x-heep#253) (Hossein Taji) * add interleaved bus (esl-epfl/x-heep#237) (Daniel Vázquez) * fix parameters when there are no external domains (esl- epfl/x-heep#247) (Davide Schiavone) * Corrected two comments and removed the FIC part in the power gating example. (esl-epfl/x-heep#248) (JuanSapriza) * make example external periph shorter (esl-epfl/x-heep#232) (Davide Schiavone) * Minor modification on Readme (esl-epfl/x-heep#245) (jmiranda) * Fixing APPs and Compilation issues + FreeRTOS HEAP mem (esl- epfl/x-heep#238) (jmiranda) * updating fast intr ctrl based on structure (esl-epfl/x-heep#235) (Hossein Taji) * [hw] adding peripheral inclusion/exclusion configuration (esl- epfl/x-heep#244) (Davide Schiavone) * add PDM2PCM peripheral (esl-epfl/x-heep#192) (grinningmosfet) * Peripherals struct multireg and address mismatch fix (esl- epfl/x-heep#234) (Stefano Albini) * fix for VCS (esl-epfl/x-heep#229) (Cyril) * Build external sources with external drivers (esl-epfl/x-heep#227) (JuanSapriza) * add verilator run app command (esl-epfl/x-heep#228) (Tim Frey) Signed-off-by: Juan Sapriza <[email protected]> * Reformated files * Update esl_epfl_x_heep to esl-epfl/x-heep@9eb9c1c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 9eb9c1c61fc4cbd0502d58f3dc1c43e07f1f7018 Signed-off-by: Juan Sapriza <[email protected]> * formatted with verible * Added verible command to mcu-gen, which was lost * Modified the README to direct to the vendorized X-HEEP prerequisistes * Corrected a typo * Removed unnecessary content from core * Updated the mcu-gen of the topmost Makefile to call the one from X-HEEP and only afterwards call the mc_gen.py with the testbench. * Changed the EXT_XBAR_NMASTER param for EXT_DOMAINS_RND to comply with the changes of #247. Now mcu-gen EXTERNAL_DOMAINS=4 is needed. Also had to add dummy (unused) logic variables or otherwise a variable would be flagged as unused. * Improved the names of the dummy variables * Moved the xilinx_cgra_x_heep_wrapper int othe fpga_cgra folder. * Updated vendor file * Update esl_epfl_x_heep to esl-epfl/x-heep@a22056c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision a22056c135460b3eb5193caf2fce7e431230393f * fix esl-epfl/x-heep#291 (esl-epfl/x-heep#292) (Davide Schiavone) * fix example_power_gating_core app (esl-epfl/x-heep#286) (Simone Machetti) * fix esl-epfl/x-heep#266 and esl-epfl/x-heep#289 (esl- epfl/x-heep#290) (Davide Schiavone) * Added compilation warning. (esl-epfl/x-heep#287) (Simone Machetti) * fix Linux FEMU (esl-epfl/x-heep#285) (Simone Machetti) * added logo (esl-epfl/x-heep#283) (Simone Machetti) * update cv32e40p (esl-epfl/x-heep#269) (Davide Schiavone) * Add makefile variable for compiler prefix (esl-epfl/x-heep#278) (David Mallasén Quintana) * CI to verify that apps can be built on every push/PR (esl- epfl/x-heep#239) (JuanSapriza) * App fix + sh compilation script (esl-epfl/x-heep#267) (jmiranda) * update common cells (esl-epfl/x-heep#262) (Davide Schiavone) * crt logic update + CMake backend modifications (esl-epfl/x-heep#264) (jmiranda) * External peripheral app bug fix and refactor (esl-epfl/x-heep#259) (Stefano Albini) * Update CMakebackend (esl-epfl/x-heep#258) (jmiranda) * rv_plic HAL refactor (esl-epfl/x-heep#240) (Stefano Albini) Signed-off-by: Juan Sapriza <[email protected]> * Added the CGRA PLIC interrupt * CGRA dbl search working * cgra functional test working * Do not continue with mcu-gen if there was an error * Updated names to comply with changes in X-HEEP * Changed the use of EXTERNAL_DOMAINS back to EXT_XBAR_NMASTER in cgra_x_heep_top * Can be implemented, but chraseh on CGRA memory access * Crashes on read * :wip: fix external domain * almost fix vendor * add .venv symbolink link * Updated vendor file * Update esl_epfl_x_heep to esl-epfl/x-heep@435c869 Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 435c869a6861f71a045d91464cdedbcf6d1777e7 * Interrupt ID to the intr handlers of the PLIC (esl-epfl/x-heep#315) (JuanSapriza) * add ports to DMA to write to addresses coming from port2 of DMA (esl-epfl/x-heep#320) (Davide Schiavone) * DMA HAL - clean PR (esl-epfl/x-heep#317) (JuanSapriza) * Cleaning up flags (esl-epfl/x-heep#316) (Davide Schiavone) * Add support for externally defined external pads in `Makefile` (esl- epfl/x-heep#312) (Michele Caon) * Linker load flash refactor fill memory (esl-epfl/x-heep#294) (jmiranda) * add i2s peripheral (esl-epfl/x-heep#203) (Tim Frey) * Add example ADC schematic (esl-epfl/x-heep#309) (Cyril) * Update `cv32e40x` version to `0.9.0` (esl-epfl/x-heep#308) (Michele Caon) * integration of an AMS peripheral example (esl-epfl/x-heep#270) (Cyril) * Update FuseSoC remote (esl-epfl/x-heep#307) (Michele Caon) * fix USE_SPI_FLASH for FPGA (esl-epfl/x-heep#301) (Davide Schiavone) * add ifdef peripheral included (esl-epfl/x-heep#288) (Davide Schiavone) * Added command in CI to include all peripherals before building. (esl-epfl/x-heep#293) (JuanSapriza) Signed-off-by: Juan Sapriza <[email protected]> * Removed virtual environment that was being pushed. Updated pins from new peripherals in X-HEEp * Successfully simulated i nverilator * cgra_func_test working on verilator * Both apps working on FPGA * Updated lint CI to make venv * Added the venv activation * Added non-picocom option to run on the FPGA * Added comment on how to run on fpga in the README file * Remove unused top parameter for external devices. * Verible formating and x-heep tb linked file removed. Automatically generated tb utils file removed. * Append target dependency to app and clean-app to create a link in the sw folder for simpler acces to compiled files. * Added default project name to build app. * README udpated. * README cleaned. * Undo wrong change on vendor file. * Makefile update for questasim run target. * Updated Makefile and README for questasim. * reverting change to cmake targets.mak. * Solving problem with Makefile target dependencies not working. * typos corrected in CGRA code. --------- Signed-off-by: Juan Sapriza <[email protected]> Co-authored-by: Benoît Denkinger <[email protected]>

Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 086884bed017d7778d1c6309533fdf0505a220e2 * Improved the comments on the eXtendingHEEP readme (esl- epfl/x-heep#360) (JuanSapriza) * Modified the way of realizing if an app is external or not (JuanSapriza) * add script to simulate all apps (esl-epfl/x-heep#341) (JuanSapriza) * [app] fix APPs on flash_exec (esl-epfl/x-heep#357) (Davide Schiavone) * adding attributes and mux pad parameters in mcu-gen (esl- epfl/x-heep#349) (Davide Schiavone) * change signal names in power manager to reflex polarity (esl- epfl/x-heep#352) (Simone Machetti) * fix power gating core app (esl-epfl/x-heep#355) (Davide Schiavone) * add cv32e40px (esl-epfl/x-heep#353) (Davide Schiavone) * moved fpnew in its own directory (esl-epfl/x-heep#351) (Davide Schiavone) * update cv32e40p divider (esl-epfl/x-heep#350) (Davide Schiavone) * fix external pad gen (esl-epfl/x-heep#346) (Davide Schiavone) * fix mcu-gen (esl-epfl/x-heep#345) (Davide Schiavone) * update GPIO driver (esl-epfl/x-heep#246) (Hossein Taji) * fix interleaved bus (esl-epfl/x-heep#340) (Daniel Vázquez) * fix esl-epfl/x-heep#338 (esl-epfl/x-heep#339) (Davide Schiavone) * Initialized variables to 0 inside functions. Removed printf comments (esl-epfl/x-heep#334) (JuanSapriza) * made the dma_is_ready() function non-optimizable at all. (esl- epfl/x-heep#333) (JuanSapriza) * fix SPI apps (esl-epfl/x-heep#327) (Davide Schiavone) * Include x-heep.h to all apps that need it (esl-epfl/x-heep#329) (JuanSapriza) * Added soc_ctrl-reg_top warning to waiver (esl-epfl/x-heep#326) (JuanSapriza) * fix several applications (esl-epfl/x-heep#325) (Davide Schiavone) * Tries to use cmake3. If that is not available, go ahead with cmake (esl-epfl/x-heep#323) (JuanSapriza) * Improve the timing of cv32e40x by removing the debug triggers (esl- epfl/x-heep#324) (David Mallasén Quintana) * refactoring of examples (esl-epfl/x-heep#322) (JuanSapriza) * expose internal master ports to external devices (esl- epfl/x-heep#268) (Michele Caon) * Interrupt ID to the intr handlers of the PLIC (esl-epfl/x-heep#315) (JuanSapriza) * add ports to DMA to write to addresses coming from port2 of DMA (esl-epfl/x-heep#320) (Davide Schiavone) * DMA HAL - clean PR (esl-epfl/x-heep#317) (JuanSapriza) * Cleaning up flags (esl-epfl/x-heep#316) (Davide Schiavone) * Add support for externally defined external pads in `Makefile` (esl- epfl/x-heep#312) (Michele Caon) * Linker load flash refactor fill memory (esl-epfl/x-heep#294) (jmiranda) * add i2s peripheral (esl-epfl/x-heep#203) (Tim Frey) * Add example ADC schematic (esl-epfl/x-heep#309) (Cyril) * Update `cv32e40x` version to `0.9.0` (esl-epfl/x-heep#308) (Michele Caon) * integration of an AMS peripheral example (esl-epfl/x-heep#270) (Cyril) * Update FuseSoC remote (esl-epfl/x-heep#307) (Michele Caon) * fix USE_SPI_FLASH for FPGA (esl-epfl/x-heep#301) (Davide Schiavone) * add ifdef peripheral included (esl-epfl/x-heep#288) (Davide Schiavone) * Added command in CI to include all peripherals before building. (esl-epfl/x-heep#293) (JuanSapriza) * fix esl-epfl/x-heep#291 (esl-epfl/x-heep#292) (Davide Schiavone) * fix example_power_gating_core app (esl-epfl/x-heep#286) (Simone Machetti) * fix esl-epfl/x-heep#266 and esl-epfl/x-heep#289 (esl- epfl/x-heep#290) (Davide Schiavone) * Added compilation warning. (esl-epfl/x-heep#287) (Simone Machetti) * fix Linux FEMU (esl-epfl/x-heep#285) (Simone Machetti) * added logo (esl-epfl/x-heep#283) (Simone Machetti) * update cv32e40p (esl-epfl/x-heep#269) (Davide Schiavone) * Add makefile variable for compiler prefix (esl-epfl/x-heep#278) (David Mallasén Quintana) * CI to verify that apps can be built on every push/PR (esl- epfl/x-heep#239) (JuanSapriza) * App fix + sh compilation script (esl-epfl/x-heep#267) (jmiranda) * update common cells (esl-epfl/x-heep#262) (Davide Schiavone) * crt logic update + CMake backend modifications (esl-epfl/x-heep#264) (jmiranda) * External peripheral app bug fix and refactor (esl-epfl/x-heep#259) (Stefano Albini) * Update CMakebackend (esl-epfl/x-heep#258) (jmiranda) * rv_plic HAL refactor (esl-epfl/x-heep#240) (Stefano Albini) * Add LICENSE (davide schiavone) * Add F-HEEP to the eXtendingHEEP list (esl-epfl/x-heep#257) (David Mallasén Quintana) * add fast interrupt enable register (esl-epfl/x-heep#256) (Tim Frey) * improved interrupt integration (esl-epfl/x-heep#255) (Tim Frey) * Peripherals structs _reserved fields renaming (esl-epfl/x-heep#254) (Stefano Albini) * adding bitfield_read/write functions (esl-epfl/x-heep#253) (Hossein Taji) * add interleaved bus (esl-epfl/x-heep#237) (Daniel Vázquez) * fix parameters when there are no external domains (esl- epfl/x-heep#247) (Davide Schiavone) * Corrected two comments and removed the FIC part in the power gating example. (esl-epfl/x-heep#248) (JuanSapriza) * make example external periph shorter (esl-epfl/x-heep#232) (Davide Schiavone) * Minor modification on Readme (esl-epfl/x-heep#245) (jmiranda) * Fixing APPs and Compilation issues + FreeRTOS HEAP mem (esl- epfl/x-heep#238) (jmiranda) * updating fast intr ctrl based on structure (esl-epfl/x-heep#235) (Hossein Taji) * [hw] adding peripheral inclusion/exclusion configuration (esl- epfl/x-heep#244) (Davide Schiavone) * add PDM2PCM peripheral (esl-epfl/x-heep#192) (grinningmosfet) * Peripherals struct multireg and address mismatch fix (esl- epfl/x-heep#234) (Stefano Albini) * fix for VCS (esl-epfl/x-heep#229) (Cyril) * Build external sources with external drivers (esl-epfl/x-heep#227) (JuanSapriza) * add verilator run app command (esl-epfl/x-heep#228) (Tim Frey) * add tc_clk_xor2 (esl-epfl/x-heep#225) (Tim Frey) * fix venv / conda envs (esl-epfl/x-heep#221) (Davide Schiavone) * update common cells (esl-epfl/x-heep#223) (Davide Schiavone) Signed-off-by: Juan Sapriza <[email protected]>

* Updated README file to refer to x-heep repo documentation. * Corrected a typo * Made the link specific to prequisite section * Modified vendor hjson * Update esl_epfl_x_heep to esl-epfl/x-heep@495ad7a Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 495ad7ac19c2bfd6a0cc8c68deafccdfb2f7da3b * update docs (esl-epfl/x-heep#209) (David Mallasén Quintana) * Automatisation of CMake back-end (esl-epfl/x-heep#207) (jmiranda) * Add initial guide on extending X-HEEP with CORE-V-XIF (esl- epfl/x-heep#205) (David Mallasén Quintana) * update app (davide schiavone) * update debug.md (Davide Schiavone) * add FreeRTOS support and CMake compatible sw compilation (esl- epfl/x-heep#191) (jmiranda) * add support for cv32e40x (esl-epfl/x-heep#197) (David Mallasén Quintana) * fix common cell (davide schiavone) * [wip] add support for SkyWater130 and OpenRoad (esl-epfl/x-heep#181) (Davide Schiavone) * add Linux-hosted fpga emulation platform (femu) (esl- epfl/x-heep#189) (Saverio Nasturzio) * fix stepi on cve2 (Schiavone Pasquale Davide) * automatic structs generation (esl-epfl/x-heep#196) (Stefano Albini) * automate peripheral integration (esl-epfl/x-heep#195) (fimtrey) * new gpio from pulp (esl-epfl/x-heep#186) (Davide Schiavone) * clock-gating of peripheral subsystem and memory banks (esl- epfl/x-heep#187) (Saverio Nasturzio) * Auto create virtualenv for FuseSoC + other python scripts (esl- epfl/x-heep#188) (Manuel Eggimann) * fix apps and linker script (esl-epfl/x-heep#176) (Simone Machetti) * add spi2 in peripheral domain (esl-epfl/x-heep#180) (Davide Schiavone) * Fixed error in block diagram. (esl-epfl/x-heep#178) (Simone Machetti) * Update README.md (Davide Schiavone) * Added block diagrams. (esl-epfl/x-heep#177) (Simone Machetti) * Update README.md (Davide Schiavone) Signed-off-by: Juan Sapriza <[email protected]> * Modified internal sw structure * Modified folder structure to be compatible with the new compilation flow * renamed the x-heep vendor files * Update esl_epfl_x_heep to esl-epfl/x-heep@c87d7ea Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision c87d7ea9888a4353177b76b790019cf1c0c2c481 * add sw build from external (esl-epfl/x-heep#217) (JuanSapriza) * Update OpenTitan doc links in README.md (esl-epfl/x-heep#216) (ruben-roalvarez) * Removed bit-fields from peripherlas' structs generation (esl- epfl/x-heep#213) (Stefano Albini) * fix esl-epfl/x-heep#71 (Davide Schiavone) * Automate interrupt integration (esl-epfl/x-heep#202) (fimtrey) * Add LLVM-Clang support (esl-epfl/x-heep#208) (David Mallasén Quintana) * Update OpenRoadFlow.md (Davide Schiavone) * Fix questasim simulation with flash (esl-epfl/x-heep#211) (David Mallasén Quintana) Signed-off-by: Juan Sapriza <[email protected]> * Added vendor file (was not untracked before). * Major changes to make the cgra code compile * Made the necessary changes for verilator-sim to work * Updated a name in func_test main.c * It is possible to simulate a test from uppermost source folder, with cgra, via make run PROJECT=cgra_dbl_search * Compiles both CGRA apps, now includes .c files in the project folder * Made changes in Compilation flow to include files from linked folders. * Reduced the CMakeLists to make it more scalable. * Cleaned up the CMakelists a bit * Added / around the folder criteria to add files to list to prevent files with keywords in the name from being added. * Updated the CMakelist to match changes done in x-heep branch (not yet merged, but to prevent missing this by mistake) * Updated the vendor file to include a specific SHA * Update esl_epfl_x_heep to esl-epfl/x-heep@95256ea Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 95256ea6f01b665222be18c05ead2da1303729b8 * add tc_clk_xor2 (esl-epfl/x-heep#225) (Tim Frey) * fix venv / conda envs (esl-epfl/x-heep#221) (Davide Schiavone) * update common cells (esl-epfl/x-heep#223) (Davide Schiavone) * Add pynq-z2 board files (esl-epfl/x-heep#212) (David Mallasén Quintana) * Fixed two bugs (OBJ_PATH for clang and creeation of links). (esl- epfl/x-heep#222) (JuanSapriza) * add sw build from external (esl-epfl/x-heep#217) (JuanSapriza) * Update OpenTitan doc links in README.md (esl-epfl/x-heep#216) (ruben-roalvarez) * Removed bit-fields from peripherlas' structs generation (esl- epfl/x-heep#213) (Stefano Albini) * fix esl-epfl/x-heep#71 (Davide Schiavone) * Automate interrupt integration (esl-epfl/x-heep#202) (fimtrey) * Add LLVM-Clang support (esl-epfl/x-heep#208) (David Mallasén Quintana) * Update OpenRoadFlow.md (Davide Schiavone) * Fix questasim simulation with flash (esl-epfl/x-heep#211) (David Mallasén Quintana) Signed-off-by: Juan Sapriza <[email protected]> * updated the README to point to the vendorized documentation. * Updated vendor file to add fpga board files * Update esl_epfl_x_heep to esl-epfl/x-heep@158a70c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 158a70c92b16a7ab207fe25eae6e131e461d631d * Add pynq-z2 board files (esl-epfl/x-heep#212) (David Mallasén Quintana) * Fixed two bugs (OBJ_PATH for clang and creeation of links). (esl- epfl/x-heep#222) (JuanSapriza) Signed-off-by: Juan Sapriza <[email protected]> * In this configuration it is possible to make vivado-fpga. CGRA working on FPGA * Cleaned the files modified for the synthesis for fpga * Restored the CGRA files to they original values and added external cgra_fpga files. Synthezised and tested on FPGA * Removed some changes done inside the cgra * Fixed some names that were modified in previous commits. * Removed visibility signals where they didnt belong so it could be built for simulation * Removed unnecessary signals * Added some commands to quickly load into the fpga * Added the venv to the gitignore * Moved the core and added the kernel applications * Removed rand because was not allwing to build * Can run bitcount. Removed unnecessary printfs * Updated the gsm project structure * Added gsm folder * Restructured how kernels are organized in folders. * Restructure is working, but gets errors * Restructure is working, but gets errors * Stats are reported both in tabbed and latex format * Produces a neat outut with average and variance values * Made 250 iterations. Dies @ 500 * Now values are presented in cycles * Prints the ratio between cgra and software execution * Addded utility scripts * Added a plot to see the active cycles distribution in time * Previous to trying new generator * Multiple kernels are run, but results vary in unomalous ways * added edadk.conf and env.sh * Added scripts for simulation and synthesis. Problemas with including packages * Multiple kernels cannot be run one after the other * Can make questasim-sim suceesfully * Added pin toggle and reduced the number of unneccessary printfs * Gets the cycle count considering the delay of writing register. Accurate ~3 cycles * Now prints std deviation instead of variance * Added a larger access flat cost to match. Timer cycles match reported cycles. * Added the reversebit kernel. Runs, but no in conjuntion with other kernels. It seems they are not re-configuring * Reorganized the process of launching kernels, but the second kernel is not configured * Change the kernel id on each kernel change. Now they cofigure properly. Added the possibility of configuring the vcd trigger by gpio * Moved functions to kernel commons. Fixed sqrt. Fixed some lucky situations concerning interrupts. GSM can break if a printf is put between the kernel launch and the wait for interrupt. * Major refactoring and commenting of the heeptest_gen.py. Generated and added sha2, but results in errors. * GSM is working with new changes in heeptest_gen * Changed the information of the sha2 io.json and the heeptest_gen so that the cgra_output is taken from the correct field * With the modifications in the io.json and heeptest_gen every kernel is running without errors. * From the kernel common header you can choose to print all the cgra results and the comparison with software * Added sha and sqrt, but none of them work properly * Rebuilt the old kernels so that they are all under the same script. Had to fix io.json of gsm that was working because there was a bug and the in vars had depth 1 * bitcount, reversebits, sha2 and gsm without errors * bitcount, reversebits, gsm, sha and sha2 work. Only 4 kernels work toghether, the fifth gets stuck or returns errors. * Modified path to kernel_commons from header template * Intermediate commit * Corrected gsm kernel. Addd a debug option for sqrt, which is not working. Added watchdog for broken kernels. * To test on Questasim * Some modification on the patch modelsim * Made some modifications to the strsearch function and source file to debug * Adapted the way of accessing inputs and outputs from the kernel_commons. GSM works with old confi now. Must re-do all kernels * Sqrt inputs limited to positive numbers * All kernels working independently, but not toghther * imem is now a constant, but still not many kernels can be run at the same time * 6 kernels can be run, but only up to 5 iterations, no prints apart from the summaries. Bitcount is broken * All kernels can be run, up to 5 iterations * Beginning of stringsearch tests * Made some modifications to the instr-encoder so that the strsearch kernel could be re-generated. Now it runs, but gives a wrong answer * C function is working * C function is working * To test signals * Passing patlen -2 allows strsearch to finish properly, but always returns skip2 * With the corrected kernel assembly the str search kernels seems to work * Stringsearch working, but lowercase conversion failing * string search is generally working. Only starnge case in last commit is pending * Tests with fixed patterns * Fixed pattern tests with updated assembly from USI * Updated CMakeLists.txt file from x-heep to allow seemless building of apps in the x-heep repo * Added the License file * Moved the cgra-x_heep_core to the base folder, as it was preventing the make vivado-fpga * Re-generated the bitstream from the assembly from USI * Added fixed arrays for testing * reverted changes to cgra.sv * Added the exit command to the assembly, which was causing the app to crash * Patched scrit and added core to allow questasim-sim-opt * Updated the bitstream to a working one * Added changes in logic of RCs. Still changing last value of result RC * Cleaned the modifications in the cgra.sv file. This works both on Questasim and FPGA. * Brought changes tested on kernel_test_sim to to use in the FPGA * The 7 kernels can be run on the pynq-z2 * Removed wrong comment * Renamed vendor files for consistency with lint checks * Updated the vendor sha * Update esl_epfl_x_heep to esl-epfl/x-heep@9eb9c1c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 9eb9c1c61fc4cbd0502d58f3dc1c43e07f1f7018 * Add LICENSE (davide schiavone) * Add F-HEEP to the eXtendingHEEP list (esl-epfl/x-heep#257) (David Mallasén Quintana) * add fast interrupt enable register (esl-epfl/x-heep#256) (Tim Frey) * improved interrupt integration (esl-epfl/x-heep#255) (Tim Frey) * Peripherals structs _reserved fields renaming (esl-epfl/x-heep#254) (Stefano Albini) * adding bitfield_read/write functions (esl-epfl/x-heep#253) (Hossein Taji) * add interleaved bus (esl-epfl/x-heep#237) (Daniel Vázquez) * fix parameters when there are no external domains (esl- epfl/x-heep#247) (Davide Schiavone) * Corrected two comments and removed the FIC part in the power gating example. (esl-epfl/x-heep#248) (JuanSapriza) * make example external periph shorter (esl-epfl/x-heep#232) (Davide Schiavone) * Minor modification on Readme (esl-epfl/x-heep#245) (jmiranda) * Fixing APPs and Compilation issues + FreeRTOS HEAP mem (esl- epfl/x-heep#238) (jmiranda) * updating fast intr ctrl based on structure (esl-epfl/x-heep#235) (Hossein Taji) * [hw] adding peripheral inclusion/exclusion configuration (esl- epfl/x-heep#244) (Davide Schiavone) * add PDM2PCM peripheral (esl-epfl/x-heep#192) (grinningmosfet) * Peripherals struct multireg and address mismatch fix (esl- epfl/x-heep#234) (Stefano Albini) * fix for VCS (esl-epfl/x-heep#229) (Cyril) * Build external sources with external drivers (esl-epfl/x-heep#227) (JuanSapriza) * add verilator run app command (esl-epfl/x-heep#228) (Tim Frey) Signed-off-by: Juan Sapriza <[email protected]> * Reformated files * Update esl_epfl_x_heep to esl-epfl/x-heep@9eb9c1c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 9eb9c1c61fc4cbd0502d58f3dc1c43e07f1f7018 Signed-off-by: Juan Sapriza <[email protected]> * formatted with verible * Added verible command to mcu-gen, which was lost * Modified the README to direct to the vendorized X-HEEP prerequisistes * Corrected a typo * Removed unnecessary content from core * Updated the mcu-gen of the topmost Makefile to call the one from X-HEEP and only afterwards call the mc_gen.py with the testbench. * Changed the EXT_XBAR_NMASTER param for EXT_DOMAINS_RND to comply with the changes of #247. Now mcu-gen EXTERNAL_DOMAINS=4 is needed. Also had to add dummy (unused) logic variables or otherwise a variable would be flagged as unused. * Improved the names of the dummy variables * Moved the xilinx_cgra_x_heep_wrapper int othe fpga_cgra folder. * Fixed the computation of the deviation. Still some differences with post-synthesis simulation * Added the generation of new VCD files by toggling of GPIO * Adapted for FPGA. Running * Re-adapted the value to be substarcted to the time measured * Updated vendor file * Update esl_epfl_x_heep to esl-epfl/x-heep@a22056c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision a22056c135460b3eb5193caf2fce7e431230393f * fix esl-epfl/x-heep#291 (esl-epfl/x-heep#292) (Davide Schiavone) * fix example_power_gating_core app (esl-epfl/x-heep#286) (Simone Machetti) * fix esl-epfl/x-heep#266 and esl-epfl/x-heep#289 (esl- epfl/x-heep#290) (Davide Schiavone) * Added compilation warning. (esl-epfl/x-heep#287) (Simone Machetti) * fix Linux FEMU (esl-epfl/x-heep#285) (Simone Machetti) * added logo (esl-epfl/x-heep#283) (Simone Machetti) * update cv32e40p (esl-epfl/x-heep#269) (Davide Schiavone) * Add makefile variable for compiler prefix (esl-epfl/x-heep#278) (David Mallasén Quintana) * CI to verify that apps can be built on every push/PR (esl- epfl/x-heep#239) (JuanSapriza) * App fix + sh compilation script (esl-epfl/x-heep#267) (jmiranda) * update common cells (esl-epfl/x-heep#262) (Davide Schiavone) * crt logic update + CMake backend modifications (esl-epfl/x-heep#264) (jmiranda) * External peripheral app bug fix and refactor (esl-epfl/x-heep#259) (Stefano Albini) * Update CMakebackend (esl-epfl/x-heep#258) (jmiranda) * rv_plic HAL refactor (esl-epfl/x-heep#240) (Stefano Albini) Signed-off-by: Juan Sapriza <[email protected]> * Added the CGRA PLIC interrupt * CGRA dbl search working * cgra functional test working * Do not continue with mcu-gen if there was an error * Updated names to comply with changes in X-HEEP * Changed the use of EXTERNAL_DOMAINS back to EXT_XBAR_NMASTER in cgra_x_heep_top * Can be implemented, but chraseh on CGRA memory access * Crashes on read * :wip: fix external domain * almost fix vendor * add .venv symbolink link * Updated vendor file * Update esl_epfl_x_heep to esl-epfl/x-heep@435c869 Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 435c869a6861f71a045d91464cdedbcf6d1777e7 * Interrupt ID to the intr handlers of the PLIC (esl-epfl/x-heep#315) (JuanSapriza) * add ports to DMA to write to addresses coming from port2 of DMA (esl-epfl/x-heep#320) (Davide Schiavone) * DMA HAL - clean PR (esl-epfl/x-heep#317) (JuanSapriza) * Cleaning up flags (esl-epfl/x-heep#316) (Davide Schiavone) * Add support for externally defined external pads in `Makefile` (esl- epfl/x-heep#312) (Michele Caon) * Linker load flash refactor fill memory (esl-epfl/x-heep#294) (jmiranda) * add i2s peripheral (esl-epfl/x-heep#203) (Tim Frey) * Add example ADC schematic (esl-epfl/x-heep#309) (Cyril) * Update `cv32e40x` version to `0.9.0` (esl-epfl/x-heep#308) (Michele Caon) * integration of an AMS peripheral example (esl-epfl/x-heep#270) (Cyril) * Update FuseSoC remote (esl-epfl/x-heep#307) (Michele Caon) * fix USE_SPI_FLASH for FPGA (esl-epfl/x-heep#301) (Davide Schiavone) * add ifdef peripheral included (esl-epfl/x-heep#288) (Davide Schiavone) * Added command in CI to include all peripherals before building. (esl-epfl/x-heep#293) (JuanSapriza) Signed-off-by: Juan Sapriza <[email protected]> * Removed virtual environment that was being pushed. Updated pins from new peripherals in X-HEEp * Successfully simulated i nverilator * cgra_func_test working on verilator * Both apps working on FPGA * Updated lint CI to make venv * Added the venv activation * Added non-picocom option to run on the FPGA * Added comment on how to run on fpga in the README file * Updated so to run apps in the FPGA * Kernel test working for 4x4 * Convolution running sucessfully in software * Added a 3x3 convolution - most basic example * Test for convolution * Fixed conflict in tb * Added temporary register to verilator waiver * Updated the links to the tb_top * Removed a vscode folder --------- Signed-off-by: Juan Sapriza <[email protected]> Co-authored-by: Sapriza Juan <[email protected]>

* Updated README file to refer to x-heep repo documentation. * Corrected a typo * Made the link specific to prequisite section * Modified vendor hjson * Update esl_epfl_x_heep to esl-epfl/x-heep@495ad7a Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 495ad7ac19c2bfd6a0cc8c68deafccdfb2f7da3b * update docs (esl-epfl/x-heep#209) (David Mallasén Quintana) * Automatisation of CMake back-end (esl-epfl/x-heep#207) (jmiranda) * Add initial guide on extending X-HEEP with CORE-V-XIF (esl- epfl/x-heep#205) (David Mallasén Quintana) * update app (davide schiavone) * update debug.md (Davide Schiavone) * add FreeRTOS support and CMake compatible sw compilation (esl- epfl/x-heep#191) (jmiranda) * add support for cv32e40x (esl-epfl/x-heep#197) (David Mallasén Quintana) * fix common cell (davide schiavone) * [wip] add support for SkyWater130 and OpenRoad (esl-epfl/x-heep#181) (Davide Schiavone) * add Linux-hosted fpga emulation platform (femu) (esl- epfl/x-heep#189) (Saverio Nasturzio) * fix stepi on cve2 (Schiavone Pasquale Davide) * automatic structs generation (esl-epfl/x-heep#196) (Stefano Albini) * automate peripheral integration (esl-epfl/x-heep#195) (fimtrey) * new gpio from pulp (esl-epfl/x-heep#186) (Davide Schiavone) * clock-gating of peripheral subsystem and memory banks (esl- epfl/x-heep#187) (Saverio Nasturzio) * Auto create virtualenv for FuseSoC + other python scripts (esl- epfl/x-heep#188) (Manuel Eggimann) * fix apps and linker script (esl-epfl/x-heep#176) (Simone Machetti) * add spi2 in peripheral domain (esl-epfl/x-heep#180) (Davide Schiavone) * Fixed error in block diagram. (esl-epfl/x-heep#178) (Simone Machetti) * Update README.md (Davide Schiavone) * Added block diagrams. (esl-epfl/x-heep#177) (Simone Machetti) * Update README.md (Davide Schiavone) Signed-off-by: Juan Sapriza <[email protected]> * Modified internal sw structure * Modified folder structure to be compatible with the new compilation flow * renamed the x-heep vendor files * Update esl_epfl_x_heep to esl-epfl/x-heep@c87d7ea Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision c87d7ea9888a4353177b76b790019cf1c0c2c481 * add sw build from external (esl-epfl/x-heep#217) (JuanSapriza) * Update OpenTitan doc links in README.md (esl-epfl/x-heep#216) (ruben-roalvarez) * Removed bit-fields from peripherlas' structs generation (esl- epfl/x-heep#213) (Stefano Albini) * fix esl-epfl/x-heep#71 (Davide Schiavone) * Automate interrupt integration (esl-epfl/x-heep#202) (fimtrey) * Add LLVM-Clang support (esl-epfl/x-heep#208) (David Mallasén Quintana) * Update OpenRoadFlow.md (Davide Schiavone) * Fix questasim simulation with flash (esl-epfl/x-heep#211) (David Mallasén Quintana) Signed-off-by: Juan Sapriza <[email protected]> * Added vendor file (was not untracked before). * Major changes to make the cgra code compile * Made the necessary changes for verilator-sim to work * Updated a name in func_test main.c * It is possible to simulate a test from uppermost source folder, with cgra, via make run PROJECT=cgra_dbl_search * Compiles both CGRA apps, now includes .c files in the project folder * Made changes in Compilation flow to include files from linked folders. * Reduced the CMakeLists to make it more scalable. * Cleaned up the CMakelists a bit * Added / around the folder criteria to add files to list to prevent files with keywords in the name from being added. * Updated the CMakelist to match changes done in x-heep branch (not yet merged, but to prevent missing this by mistake) * Updated the vendor file to include a specific SHA * Update esl_epfl_x_heep to esl-epfl/x-heep@95256ea Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 95256ea6f01b665222be18c05ead2da1303729b8 * add tc_clk_xor2 (esl-epfl/x-heep#225) (Tim Frey) * fix venv / conda envs (esl-epfl/x-heep#221) (Davide Schiavone) * update common cells (esl-epfl/x-heep#223) (Davide Schiavone) * Add pynq-z2 board files (esl-epfl/x-heep#212) (David Mallasén Quintana) * Fixed two bugs (OBJ_PATH for clang and creeation of links). (esl- epfl/x-heep#222) (JuanSapriza) * add sw build from external (esl-epfl/x-heep#217) (JuanSapriza) * Update OpenTitan doc links in README.md (esl-epfl/x-heep#216) (ruben-roalvarez) * Removed bit-fields from peripherlas' structs generation (esl- epfl/x-heep#213) (Stefano Albini) * fix esl-epfl/x-heep#71 (Davide Schiavone) * Automate interrupt integration (esl-epfl/x-heep#202) (fimtrey) * Add LLVM-Clang support (esl-epfl/x-heep#208) (David Mallasén Quintana) * Update OpenRoadFlow.md (Davide Schiavone) * Fix questasim simulation with flash (esl-epfl/x-heep#211) (David Mallasén Quintana) Signed-off-by: Juan Sapriza <[email protected]> * updated the README to point to the vendorized documentation. * Updated vendor file to add fpga board files * Update esl_epfl_x_heep to esl-epfl/x-heep@158a70c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 158a70c92b16a7ab207fe25eae6e131e461d631d * Add pynq-z2 board files (esl-epfl/x-heep#212) (David Mallasén Quintana) * Fixed two bugs (OBJ_PATH for clang and creeation of links). (esl- epfl/x-heep#222) (JuanSapriza) Signed-off-by: Juan Sapriza <[email protected]> * In this configuration it is possible to make vivado-fpga. CGRA working on FPGA * Cleaned the files modified for the synthesis for fpga * Restored the CGRA files to they original values and added external cgra_fpga files. Synthezised and tested on FPGA * Removed some changes done inside the cgra * Fixed some names that were modified in previous commits. * Removed visibility signals where they didnt belong so it could be built for simulation * Removed unnecessary signals * Added some commands to quickly load into the fpga * Added the venv to the gitignore * Moved the core and added the kernel applications * Removed rand because was not allwing to build * Can run bitcount. Removed unnecessary printfs * Updated the gsm project structure * Added gsm folder * Restructured how kernels are organized in folders. * Restructure is working, but gets errors * Restructure is working, but gets errors * Stats are reported both in tabbed and latex format * Produces a neat outut with average and variance values * Made 250 iterations. Dies @ 500 * Now values are presented in cycles * Prints the ratio between cgra and software execution * Addded utility scripts * Added a plot to see the active cycles distribution in time * Previous to trying new generator * Multiple kernels are run, but results vary in unomalous ways * added edadk.conf and env.sh * Added scripts for simulation and synthesis. Problemas with including packages * Multiple kernels cannot be run one after the other * Can make questasim-sim suceesfully * Added pin toggle and reduced the number of unneccessary printfs * Gets the cycle count considering the delay of writing register. Accurate ~3 cycles * Now prints std deviation instead of variance * Added a larger access flat cost to match. Timer cycles match reported cycles. * Added the reversebit kernel. Runs, but no in conjuntion with other kernels. It seems they are not re-configuring * Reorganized the process of launching kernels, but the second kernel is not configured * Change the kernel id on each kernel change. Now they cofigure properly. Added the possibility of configuring the vcd trigger by gpio * Moved functions to kernel commons. Fixed sqrt. Fixed some lucky situations concerning interrupts. GSM can break if a printf is put between the kernel launch and the wait for interrupt. * Major refactoring and commenting of the heeptest_gen.py. Generated and added sha2, but results in errors. * GSM is working with new changes in heeptest_gen * Changed the information of the sha2 io.json and the heeptest_gen so that the cgra_output is taken from the correct field * With the modifications in the io.json and heeptest_gen every kernel is running without errors. * From the kernel common header you can choose to print all the cgra results and the comparison with software * Added sha and sqrt, but none of them work properly * Rebuilt the old kernels so that they are all under the same script. Had to fix io.json of gsm that was working because there was a bug and the in vars had depth 1 * bitcount, reversebits, sha2 and gsm without errors * bitcount, reversebits, gsm, sha and sha2 work. Only 4 kernels work toghether, the fifth gets stuck or returns errors. * Modified path to kernel_commons from header template * Intermediate commit * Corrected gsm kernel. Addd a debug option for sqrt, which is not working. Added watchdog for broken kernels. * To test on Questasim * Some modification on the patch modelsim * Made some modifications to the strsearch function and source file to debug * Adapted the way of accessing inputs and outputs from the kernel_commons. GSM works with old confi now. Must re-do all kernels * Sqrt inputs limited to positive numbers * All kernels working independently, but not toghther * imem is now a constant, but still not many kernels can be run at the same time * 6 kernels can be run, but only up to 5 iterations, no prints apart from the summaries. Bitcount is broken * All kernels can be run, up to 5 iterations * Beginning of stringsearch tests * Made some modifications to the instr-encoder so that the strsearch kernel could be re-generated. Now it runs, but gives a wrong answer * C function is working * C function is working * To test signals * Passing patlen -2 allows strsearch to finish properly, but always returns skip2 * With the corrected kernel assembly the str search kernels seems to work * Stringsearch working, but lowercase conversion failing * string search is generally working. Only starnge case in last commit is pending * Tests with fixed patterns * Fixed pattern tests with updated assembly from USI * Updated CMakeLists.txt file from x-heep to allow seemless building of apps in the x-heep repo * Added the License file * Moved the cgra-x_heep_core to the base folder, as it was preventing the make vivado-fpga * Re-generated the bitstream from the assembly from USI * Added fixed arrays for testing * reverted changes to cgra.sv * Added the exit command to the assembly, which was causing the app to crash * Patched scrit and added core to allow questasim-sim-opt * Updated the bitstream to a working one * Added changes in logic of RCs. Still changing last value of result RC * Cleaned the modifications in the cgra.sv file. This works both on Questasim and FPGA. * Brought changes tested on kernel_test_sim to to use in the FPGA * The 7 kernels can be run on the pynq-z2 * Removed wrong comment * Renamed vendor files for consistency with lint checks * Updated the vendor sha * Update esl_epfl_x_heep to esl-epfl/x-heep@9eb9c1c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 9eb9c1c61fc4cbd0502d58f3dc1c43e07f1f7018 * Add LICENSE (davide schiavone) * Add F-HEEP to the eXtendingHEEP list (esl-epfl/x-heep#257) (David Mallasén Quintana) * add fast interrupt enable register (esl-epfl/x-heep#256) (Tim Frey) * improved interrupt integration (esl-epfl/x-heep#255) (Tim Frey) * Peripherals structs _reserved fields renaming (esl-epfl/x-heep#254) (Stefano Albini) * adding bitfield_read/write functions (esl-epfl/x-heep#253) (Hossein Taji) * add interleaved bus (esl-epfl/x-heep#237) (Daniel Vázquez) * fix parameters when there are no external domains (esl- epfl/x-heep#247) (Davide Schiavone) * Corrected two comments and removed the FIC part in the power gating example. (esl-epfl/x-heep#248) (JuanSapriza) * make example external periph shorter (esl-epfl/x-heep#232) (Davide Schiavone) * Minor modification on Readme (esl-epfl/x-heep#245) (jmiranda) * Fixing APPs and Compilation issues + FreeRTOS HEAP mem (esl- epfl/x-heep#238) (jmiranda) * updating fast intr ctrl based on structure (esl-epfl/x-heep#235) (Hossein Taji) * [hw] adding peripheral inclusion/exclusion configuration (esl- epfl/x-heep#244) (Davide Schiavone) * add PDM2PCM peripheral (esl-epfl/x-heep#192) (grinningmosfet) * Peripherals struct multireg and address mismatch fix (esl- epfl/x-heep#234) (Stefano Albini) * fix for VCS (esl-epfl/x-heep#229) (Cyril) * Build external sources with external drivers (esl-epfl/x-heep#227) (JuanSapriza) * add verilator run app command (esl-epfl/x-heep#228) (Tim Frey) Signed-off-by: Juan Sapriza <[email protected]> * Reformated files * Update esl_epfl_x_heep to esl-epfl/x-heep@9eb9c1c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 9eb9c1c61fc4cbd0502d58f3dc1c43e07f1f7018 Signed-off-by: Juan Sapriza <[email protected]> * formatted with verible * Added verible command to mcu-gen, which was lost * Modified the README to direct to the vendorized X-HEEP prerequisistes * Corrected a typo * Removed unnecessary content from core * Updated the mcu-gen of the topmost Makefile to call the one from X-HEEP and only afterwards call the mc_gen.py with the testbench. * Changed the EXT_XBAR_NMASTER param for EXT_DOMAINS_RND to comply with the changes of #247. Now mcu-gen EXTERNAL_DOMAINS=4 is needed. Also had to add dummy (unused) logic variables or otherwise a variable would be flagged as unused. * Improved the names of the dummy variables * Moved the xilinx_cgra_x_heep_wrapper int othe fpga_cgra folder. * Fixed the computation of the deviation. Still some differences with post-synthesis simulation * Added the generation of new VCD files by toggling of GPIO * Adapted for FPGA. Running * Re-adapted the value to be substarcted to the time measured * Updated vendor file * Update esl_epfl_x_heep to esl-epfl/x-heep@a22056c Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision a22056c135460b3eb5193caf2fce7e431230393f * fix esl-epfl/x-heep#291 (esl-epfl/x-heep#292) (Davide Schiavone) * fix example_power_gating_core app (esl-epfl/x-heep#286) (Simone Machetti) * fix esl-epfl/x-heep#266 and esl-epfl/x-heep#289 (esl- epfl/x-heep#290) (Davide Schiavone) * Added compilation warning. (esl-epfl/x-heep#287) (Simone Machetti) * fix Linux FEMU (esl-epfl/x-heep#285) (Simone Machetti) * added logo (esl-epfl/x-heep#283) (Simone Machetti) * update cv32e40p (esl-epfl/x-heep#269) (Davide Schiavone) * Add makefile variable for compiler prefix (esl-epfl/x-heep#278) (David Mallasén Quintana) * CI to verify that apps can be built on every push/PR (esl- epfl/x-heep#239) (JuanSapriza) * App fix + sh compilation script (esl-epfl/x-heep#267) (jmiranda) * update common cells (esl-epfl/x-heep#262) (Davide Schiavone) * crt logic update + CMake backend modifications (esl-epfl/x-heep#264) (jmiranda) * External peripheral app bug fix and refactor (esl-epfl/x-heep#259) (Stefano Albini) * Update CMakebackend (esl-epfl/x-heep#258) (jmiranda) * rv_plic HAL refactor (esl-epfl/x-heep#240) (Stefano Albini) Signed-off-by: Juan Sapriza <[email protected]> * Added the CGRA PLIC interrupt * CGRA dbl search working * cgra functional test working * Do not continue with mcu-gen if there was an error * Updated names to comply with changes in X-HEEP * Changed the use of EXTERNAL_DOMAINS back to EXT_XBAR_NMASTER in cgra_x_heep_top * Can be implemented, but chraseh on CGRA memory access * Crashes on read * :wip: fix external domain * almost fix vendor * add .venv symbolink link * Updated vendor file * Update esl_epfl_x_heep to esl-epfl/x-heep@435c869 Update code from upstream repository https://github.com/esl- epfl/x-heep.git to revision 435c869a6861f71a045d91464cdedbcf6d1777e7 * Interrupt ID to the intr handlers of the PLIC (esl-epfl/x-heep#315) (JuanSapriza) * add ports to DMA to write to addresses coming from port2 of DMA (esl-epfl/x-heep#320) (Davide Schiavone) * DMA HAL - clean PR (esl-epfl/x-heep#317) (JuanSapriza) * Cleaning up flags (esl-epfl/x-heep#316) (Davide Schiavone) * Add support for externally defined external pads in `Makefile` (esl- epfl/x-heep#312) (Michele Caon) * Linker load flash refactor fill memory (esl-epfl/x-heep#294) (jmiranda) * add i2s peripheral (esl-epfl/x-heep#203) (Tim Frey) * Add example ADC schematic (esl-epfl/x-heep#309) (Cyril) * Update `cv32e40x` version to `0.9.0` (esl-epfl/x-heep#308) (Michele Caon) * integration of an AMS peripheral example (esl-epfl/x-heep#270) (Cyril) * Update FuseSoC remote (esl-epfl/x-heep#307) (Michele Caon) * fix USE_SPI_FLASH for FPGA (esl-epfl/x-heep#301) (Davide Schiavone) * add ifdef peripheral included (esl-epfl/x-heep#288) (Davide Schiavone) * Added command in CI to include all peripherals before building. (esl-epfl/x-heep#293) (JuanSapriza) Signed-off-by: Juan Sapriza <[email protected]> * Removed virtual environment that was being pushed. Updated pins from new peripherals in X-HEEp * Successfully simulated i nverilator * cgra_func_test working on verilator * Both apps working on FPGA * Updated lint CI to make venv * Added the venv activation * Added non-picocom option to run on the FPGA * Added comment on how to run on fpga in the README file * Updated so to run apps in the FPGA * Kernel test working for 4x4 * Convolution running sucessfully in software * Added a 3x3 convolution - most basic example * Test for convolution * Fixed conflict in tb * Added temporary register to verilator waiver * Updated the links to the tb_top * Removed a vscode folder * Removed sudo from run commands on makefile and left repo running reversebits --------- Signed-off-by: Juan Sapriza <[email protected]> Co-authored-by: Sapriza Juan <[email protected]>

add ifdef peripheral included

5ffcfc0

davideschiavone requested review from JuanSapriza and JoseCalero May 26, 2023 06:11

JoseCalero requested changes May 26, 2023

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implement #error in compilation

7f5fc95

JuanSapriza mentioned this pull request May 31, 2023

Added command in CI to include all peripherals before building. #293

Merged

davideschiavone force-pushed the add_peripheral_info branch from c40acca to 7f5fc95 Compare May 31, 2023 10:49

Merge remote-tracking branch 'origin' into add_peripheral_info

831fc22

JoseCalero merged commit 7dd2b02 into esl-epfl:main May 31, 2023

davideschiavone deleted the add_peripheral_info branch February 23, 2024 15:15

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add ifdef peripheral included #288

add ifdef peripheral included #288

davideschiavone commented May 26, 2023

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JuanSapriza commented May 30, 2023 •

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JoseCalero commented May 31, 2023

davideschiavone commented May 31, 2023

add ifdef peripheral included #288

add ifdef peripheral included #288

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davideschiavone commented May 30, 2023

JuanSapriza commented May 30, 2023

davideschiavone commented May 30, 2023

JuanSapriza commented May 30, 2023

JoseCalero commented May 30, 2023

davideschiavone commented May 30, 2023

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davideschiavone commented May 30, 2023

JuanSapriza commented May 30, 2023 • edited Loading

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JuanSapriza commented May 31, 2023 •

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