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how to generate the rtl code of crossbar and dma related .py
#137
opened Jul 10, 2024 by
constant007
[Feature request] Implementation of a Root Complex
help-welcome :)
new-feature
sponsor-welcome :)
#122
opened Aug 25, 2023 by
ohault
dma_test with external loopback
answered-waiting-feedback
question
#116
opened May 29, 2023 by
vbuitvydas
Device Disconnection while
litex_term
is running hangs the kernel over thunderbolt bridge
#95
opened Apr 8, 2022 by
sjkelly
Support for Xilinx soft PCIe PHY?
help-welcome :)
new-feature
sponsor-welcome :)
#83
opened Jan 5, 2022 by
Elgox2
Add optional performance/error monitor on core's streams.
enhancement
#67
opened Dec 6, 2021 by
enjoy-digital
Move Ultrascale(+) TLP adaption code from Verilog to Migen
enhancement
help-welcome :)
sponsor-welcome :)
#42
opened Sep 23, 2020 by
enjoy-digital
Check PCIe bus rescan after loading bitstream.
add-answer-to-wiki
enhancement
#36
opened Jul 2, 2020 by
enjoy-digital
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