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The tlast signal doesn't seem to be working #131

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black-pigeon opened this issue Mar 26, 2024 · 0 comments
Open

The tlast signal doesn't seem to be working #131

black-pigeon opened this issue Mar 26, 2024 · 0 comments

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@black-pigeon
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Hello, I have started using litepcie as a means of communication between FPGA and the host in a recent project.

  • Hardware: Xilinx Artix7 200T
  • litexpcie version: The latest master branch, commit ID is 3e24f6f.

I have designed the following template according to my needs.

{
    # PHY ----------------------------------------------------------------------
    "phy"                     : "S7PCIEPHY", # Type of PCIe PHY
    "phy_device"              : "xc7a200tfbg484-2",      # Type of Device
    "phy_lanes"               : 2,           # Number of lanes
    "phy_pcie_data_width"     : 64,         # PCIe data_width
    "phy_data_width"          : 64,         # Bus data_width
    "phy_bar0_size"           : 0x40000,     # BAR0 size

    # Clocking -----------------------------------------------------------------
    "clk_freq"                : 125e6,        # User Clk Freq (AXI MMAP/DMA)
    "clk_external"            : False,         # Use external User provided Clk

    # Endpoint -----------------------------------------------------------------
    "ep_max_pending_requests" : 8,
    "ep_address_width"        : 32,

    # Control ------------------------------------------------------------------
    "ctrl"                    : False,

    # MMAP Master --------------------------------------------------------------
    "mmap"                    : False,
    "mmap_base"               : 0x00020000,
    "mmap_size"               : 0x00020000,

    # MMAP Slave ---------------------------------------------------------------
    "mmap_slave"              : False,
    "mmap_slave_axi_full"     : False,

    # DMA channels -------------------------------------------------------------
    "dma_channels"            : 4,     # Number of DMA channels
    "dma_buffering"           : 8192,  # Buffering for each channel (in bytes)
    "dma_loopback"            : True,  # Enable DMA loopback capability
    "dma_synchronizer"        : False, # Enable DMA synchronizer capability
    "dma_monitor"             : False, # Enable DMA monitoring capability

    # MSI IRQs -----------------------------------------------------------------
    "msi_irqs"                : 16, # Number or MSI IRQs
}

I have also compiled and loaded the driver correctly.

[ 5158.646924] litepcie 0000:01:00.0: [Removing device]
[ 5163.556627] litepcie 0000:01:00.0: [Probing device]
[ 5163.579759] litepcie 0000:01:00.0: Version LitePCIe standalone core 2024-03-26 13:47:48
[ 5163.579855] litepcie 0000:01:00.0: 1 MSI IRQs allocated.
[ 5163.579886] litepcie 0000:01:00.0: Creating /dev/litepcie0
[ 5163.579984] litepcie 0000:01:00.0: Creating /dev/litepcie1
[ 5163.580043] litepcie 0000:01:00.0: Creating /dev/litepcie2
[ 5163.580100] litepcie 0000:01:00.0: Creating /dev/litepcie3

I am now conducting DMA testing using the following command: sudo ./litepcie_util -c 0 -e dma_test. On the FPGA, I am using ILA to capture signals on the axis interface provided by the litepcie framework. However, I noticed that the dma0_reader_axi_tlast signal is not being set. Additionally, I observed that the dma0_reader_axi_tuser goes high for one beat at the beginning of a transfer.
图片

Is there anything I am doing wrong? I hope to receive the tlast signal, which would make my work a bit easier.
Thank you for providing this project; it has given me a quick start.

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