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Use ABI names for floating registers (#109728)
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@tomeksowi
tomeksowi authored Nov 25, 2024
1 parent 53cc1dd commit d5b6aec
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Showing 7 changed files with 67 additions and 88 deletions.
2 changes: 1 addition & 1 deletion src/coreclr/jit/compiler.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3602,7 +3602,7 @@ inline unsigned genMapFloatRegNumToRegArgNum(regNumber regNum)
#elif defined(TARGET_LOONGARCH64)
return regNum - REG_F0;
#elif defined(TARGET_RISCV64)
return regNum - REG_FLTARG_0;
return regNum - REG_FA0;
#elif defined(TARGET_ARM64)
return regNum - REG_V0;
#elif defined(UNIX_AMD64_ABI)
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4 changes: 2 additions & 2 deletions src/coreclr/jit/gentree.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -30101,7 +30101,7 @@ regNumber ReturnTypeDesc::GetABIReturnReg(unsigned idx, CorInfoCallConvExtension
var_types regType = GetReturnRegType(idx);
if (idx == 0)
{
resultReg = varTypeIsIntegralOrI(regType) ? REG_INTRET : REG_FLOATRET; // A0 or F0
resultReg = varTypeIsIntegralOrI(regType) ? REG_INTRET : REG_FLOATRET; // A0 or FA0
}
else
{
Expand All @@ -30115,7 +30115,7 @@ regNumber ReturnTypeDesc::GetABIReturnReg(unsigned idx, CorInfoCallConvExtension
else
{
assert(varTypeUsesFloatReg(regType));
resultReg = varTypeIsIntegralOrI(GetReturnRegType(0)) ? REG_FLOATRET : REG_FLOATRET_1; // F0 or F1
resultReg = varTypeIsIntegralOrI(GetReturnRegType(0)) ? REG_FLOATRET : REG_FLOATRET_1; // FA0 or FA1
}
}

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2 changes: 1 addition & 1 deletion src/coreclr/jit/lsra.cpp
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Expand Up @@ -551,7 +551,7 @@ static const regMaskTP LsraLimitSmallIntSet = (RBM_T1 | RBM_T3 | RBM_A0 | RBM_A1
static const regMaskTP LsraLimitSmallFPSet = (RBM_F0 | RBM_F1 | RBM_F2 | RBM_F8 | RBM_F9);
#elif defined(TARGET_RISCV64)
static const regMaskTP LsraLimitSmallIntSet = (RBM_T1 | RBM_T3 | RBM_A0 | RBM_A1 | RBM_T0);
static const regMaskTP LsraLimitSmallFPSet = (RBM_F0 | RBM_F1 | RBM_F2 | RBM_F8 | RBM_F9);
static const regMaskTP LsraLimitSmallFPSet = (RBM_FT0 | RBM_FT1 | RBM_FT2 | RBM_FS0 | RBM_FS1);
#else
#error Unsupported or unset target architecture
#endif // target
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66 changes: 33 additions & 33 deletions src/coreclr/jit/registerriscv64.h
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Expand Up @@ -56,39 +56,39 @@ REGALIAS(ZERO, R0)
#define FMASK(x) (1ULL << (FBASE+(x)))

/*
REGDEF(name, rnum, mask, sname) */
REGDEF(F0, 0+FBASE, FMASK(0), "f0")
REGDEF(F1, 1+FBASE, FMASK(1), "f1")
REGDEF(F2, 2+FBASE, FMASK(2), "f2")
REGDEF(F3, 3+FBASE, FMASK(3), "f3")
REGDEF(F4, 4+FBASE, FMASK(4), "f4")
REGDEF(F5, 5+FBASE, FMASK(5), "f5")
REGDEF(F6, 6+FBASE, FMASK(6), "f6")
REGDEF(F7, 7+FBASE, FMASK(7), "f7")
REGDEF(F8, 8+FBASE, FMASK(8), "f8")
REGDEF(F9, 9+FBASE, FMASK(9), "f9")
REGDEF(F10, 10+FBASE, FMASK(10), "f10")
REGDEF(F11, 11+FBASE, FMASK(11), "f11")
REGDEF(F12, 12+FBASE, FMASK(12), "f12")
REGDEF(F13, 13+FBASE, FMASK(13), "f13")
REGDEF(F14, 14+FBASE, FMASK(14), "f14")
REGDEF(F15, 15+FBASE, FMASK(15), "f15")
REGDEF(F16, 16+FBASE, FMASK(16), "f16")
REGDEF(F17, 17+FBASE, FMASK(17), "f17")
REGDEF(F18, 18+FBASE, FMASK(18), "f18")
REGDEF(F19, 19+FBASE, FMASK(19), "f19")
REGDEF(F20, 20+FBASE, FMASK(20), "f20")
REGDEF(F21, 21+FBASE, FMASK(21), "f21")
REGDEF(F22, 22+FBASE, FMASK(22), "f22")
REGDEF(F23, 23+FBASE, FMASK(23), "f23")
REGDEF(F24, 24+FBASE, FMASK(24), "f24")
REGDEF(F25, 25+FBASE, FMASK(25), "f25")
REGDEF(F26, 26+FBASE, FMASK(26), "f26")
REGDEF(F27, 27+FBASE, FMASK(27), "f27")
REGDEF(F28, 28+FBASE, FMASK(28), "f28")
REGDEF(F29, 29+FBASE, FMASK(29), "f29")
REGDEF(F30, 30+FBASE, FMASK(30), "f30")
REGDEF(F31, 31+FBASE, FMASK(31), "f31")
REGDEF(name, rnum, mask, sname) */
REGDEF(FT0, 0+FBASE, FMASK(0), "ft0")
REGDEF(FT1, 1+FBASE, FMASK(1), "ft1")
REGDEF(FT2, 2+FBASE, FMASK(2), "ft2")
REGDEF(FT3, 3+FBASE, FMASK(3), "ft3")
REGDEF(FT4, 4+FBASE, FMASK(4), "ft4")
REGDEF(FT5, 5+FBASE, FMASK(5), "ft5")
REGDEF(FT6, 6+FBASE, FMASK(6), "ft6")
REGDEF(FT7, 7+FBASE, FMASK(7), "ft7")
REGDEF(FS0, 8+FBASE, FMASK(8), "fs0")
REGDEF(FS1, 9+FBASE, FMASK(9), "fs1")
REGDEF(FA0, 10+FBASE, FMASK(10), "fa0")
REGDEF(FA1, 11+FBASE, FMASK(11), "fa1")
REGDEF(FA2, 12+FBASE, FMASK(12), "fa2")
REGDEF(FA3, 13+FBASE, FMASK(13), "fa3")
REGDEF(FA4, 14+FBASE, FMASK(14), "fa4")
REGDEF(FA5, 15+FBASE, FMASK(15), "fa5")
REGDEF(FA6, 16+FBASE, FMASK(16), "fa6")
REGDEF(FA7, 17+FBASE, FMASK(17), "fa7")
REGDEF(FS2, 18+FBASE, FMASK(18), "fs2")
REGDEF(FS3, 19+FBASE, FMASK(19), "fs3")
REGDEF(FS4, 20+FBASE, FMASK(20), "fs4")
REGDEF(FS5, 21+FBASE, FMASK(21), "fs5")
REGDEF(FS6, 22+FBASE, FMASK(22), "fs6")
REGDEF(FS7, 23+FBASE, FMASK(23), "fs7")
REGDEF(FS8, 24+FBASE, FMASK(24), "fs8")
REGDEF(FS9, 25+FBASE, FMASK(25), "fs9")
REGDEF(FS10, 26+FBASE, FMASK(26), "fs10")
REGDEF(FS11, 27+FBASE, FMASK(27), "fs11")
REGDEF(FT8, 28+FBASE, FMASK(28), "ft8")
REGDEF(FT9, 29+FBASE, FMASK(29), "ft9")
REGDEF(FT10, 30+FBASE, FMASK(30), "ft10")
REGDEF(FT11, 31+FBASE, FMASK(31), "ft11")

// The registers with values 64 (NBASE) and above are not real register numbers
#define NBASE 64
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4 changes: 2 additions & 2 deletions src/coreclr/jit/targetriscv64.cpp
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Expand Up @@ -20,8 +20,8 @@ const Target::ArgOrder Target::g_tgtUnmanagedArgOrder = ARG_ORDER_R2L;
const regNumber intArgRegs [] = {REG_A0, REG_A1, REG_A2, REG_A3, REG_A4, REG_A5, REG_A6, REG_A7};
const regMaskTP intArgMasks[] = {RBM_A0, RBM_A1, RBM_A2, RBM_A3, RBM_A4, RBM_A5, RBM_A6, RBM_A7};

const regNumber fltArgRegs [] = {REG_FLTARG_0, REG_FLTARG_1, REG_FLTARG_2, REG_FLTARG_3, REG_FLTARG_4, REG_FLTARG_5, REG_FLTARG_6, REG_FLTARG_7 };
const regMaskTP fltArgMasks[] = {RBM_FLTARG_0, RBM_FLTARG_1, RBM_FLTARG_2, RBM_FLTARG_3, RBM_FLTARG_4, RBM_FLTARG_5, RBM_FLTARG_6, RBM_FLTARG_7 };
const regNumber fltArgRegs [] = {REG_FA0, REG_FA1, REG_FA2, REG_FA3, REG_FA4, REG_FA5, REG_FA6, REG_FA7 };
const regMaskTP fltArgMasks[] = {RBM_FA0, RBM_FA1, RBM_FA2, RBM_FA3, RBM_FA4, RBM_FA5, RBM_FA6, RBM_FA7 };
// clang-format on

//-----------------------------------------------------------------------------
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67 changes: 23 additions & 44 deletions src/coreclr/jit/targetriscv64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -44,10 +44,10 @@
#define ETW_EBP_FRAMED 1 // if 1 we cannot use REG_FP as a scratch register and must setup the frame pointer for most methods
#define CSE_CONSTS 1 // Enable if we want to CSE constants

#define REG_FP_FIRST REG_F0
#define REG_FP_LAST REG_F31
#define FIRST_FP_ARGREG REG_F10
#define LAST_FP_ARGREG REG_F17
#define REG_FP_FIRST REG_FT0
#define REG_FP_LAST REG_FT11
#define FIRST_FP_ARGREG REG_FA0
#define LAST_FP_ARGREG REG_FA7

#define REGNUM_BITS 6 // number of bits in a REG_*
#define REGSIZE_BYTES 8 // number of bytes in one general purpose register
Expand All @@ -63,10 +63,10 @@
#define LAST_INT_CALLEE_SAVED REG_S11
#define RBM_INT_CALLEE_SAVED (RBM_S1|RBM_S2|RBM_S3|RBM_S4|RBM_S5|RBM_S6|RBM_S7|RBM_S8|RBM_S9|RBM_S10|RBM_S11)
#define RBM_INT_CALLEE_TRASH (RBM_A0|RBM_A1|RBM_A2|RBM_A3|RBM_A4|RBM_A5|RBM_A6|RBM_A7|RBM_T0|RBM_T1|RBM_T2|RBM_T3|RBM_T4|RBM_T5|RBM_T6)
#define FIRST_FLT_CALLEE_SAVED REG_F8
#define LAST_FLT_CALLEE_SAVED REG_F27
#define RBM_FLT_CALLEE_SAVED (RBM_F8|RBM_F9|RBM_F18|RBM_F19|RBM_F20|RBM_F21|RBM_F22|RBM_F23|RBM_F24|RBM_F25|RBM_F26|RBM_F27)
#define RBM_FLT_CALLEE_TRASH (RBM_F10|RBM_F11|RBM_F12|RBM_F13|RBM_F14|RBM_F15|RBM_F16|RBM_F17)
#define FIRST_FLT_CALLEE_SAVED REG_FS0
#define LAST_FLT_CALLEE_SAVED REG_FS11
#define RBM_FLT_CALLEE_SAVED (RBM_FS0|RBM_FS1|RBM_FS2|RBM_FS3|RBM_FS4|RBM_FS5|RBM_FS6|RBM_FS7|RBM_FS8|RBM_FS9|RBM_FS10|RBM_FS11)
#define RBM_FLT_CALLEE_TRASH (RBM_FA0|RBM_FA1|RBM_FA2|RBM_FA3|RBM_FA4|RBM_FA5|RBM_FA6|RBM_FA7|RBM_FT0|RBM_FT1|RBM_FT2|RBM_FT3|RBM_FT4|RBM_FT5|RBM_FT6|RBM_FT7|RBM_FT8|RBM_FT9|RBM_FT10|RBM_FT11)

#define RBM_CALLEE_SAVED (RBM_INT_CALLEE_SAVED | RBM_FLT_CALLEE_SAVED)
#define RBM_CALLEE_TRASH (RBM_INT_CALLEE_TRASH | RBM_FLT_CALLEE_TRASH)
Expand All @@ -83,11 +83,11 @@
REG_T0,REG_T1,REG_T2,REG_T3,REG_T4,REG_T5,REG_T6, \
REG_S1,REG_S2,REG_S3,REG_S4,REG_S5,REG_S6,REG_S7,REG_S8,REG_S9,REG_S10,REG_S11

#define REG_VAR_ORDER_FLT REG_F4, REG_F5, REG_F6, REG_F7, REG_F28, REG_F29, REG_F30, REG_F31, \
REG_F12, REG_F13, REG_F14, REG_F15, REG_F16, REG_F17, \
REG_F0, REG_F1, REG_F2, REG_F3, \
REG_F22, REG_F23, REG_F24, REG_F25, REG_F26, REG_F27, REG_F18, REG_F19, REG_F20, REG_F21, REG_F8, REG_F9, \
REG_F11, REG_F10
#define REG_VAR_ORDER_FLT REG_FT4, REG_FT5, REG_FT6, REG_FT7, REG_FT8, REG_FT9, REG_FT10, REG_FT11, \
REG_FA2, REG_FA3, REG_FA4, REG_FA5, REG_FA6, REG_FA7, \
REG_FT0, REG_FT1, REG_FT2, REG_FT3, \
REG_FS6, REG_FS7, REG_FS8, REG_FS9, REG_FS10, REG_FS11, REG_FS2, REG_FS3, REG_FS4, REG_FS5, REG_FS0, REG_FS1, \
REG_FA1, REG_FA0

#define RBM_CALL_GC_REGS_ORDER RBM_S1,RBM_S2,RBM_S3,RBM_S4,RBM_S5,RBM_S6,RBM_S7,RBM_S8,RBM_S9,RBM_S10,RBM_S11,RBM_INTRET,RBM_INTRET_1
#define RBM_CALL_GC_REGS (RBM_S1|RBM_S2|RBM_S3|RBM_S4|RBM_S5|RBM_S6|RBM_S7|RBM_S8|RBM_S9|RBM_S10|RBM_S11|RBM_INTRET|RBM_INTRET_1)
Expand Down Expand Up @@ -116,9 +116,6 @@
// This is a general scratch register that does not conflict with the argument registers
#define REG_SCRATCH REG_T0

// This is a float scratch register that does not conflict with the argument registers
#define REG_SCRATCH_FLT REG_F28

// This is a general register that can be optionally reserved for other purposes during codegen
#define REG_OPT_RSVD REG_T6
#define RBM_OPT_RSVD RBM_T6
Expand Down Expand Up @@ -208,12 +205,12 @@
#define REG_INTRET_1 REG_A1
#define RBM_INTRET_1 RBM_A1

#define REG_FLOATRET REG_F10
#define RBM_FLOATRET RBM_F10
#define RBM_DOUBLERET RBM_F10
#define REG_FLOATRET_1 REG_F11
#define RBM_FLOATRET_1 RBM_F11
#define RBM_DOUBLERET_1 RBM_F11
#define REG_FLOATRET REG_FA0
#define RBM_FLOATRET RBM_FA0
#define RBM_DOUBLERET RBM_FA0
#define REG_FLOATRET_1 REG_FA1
#define RBM_FLOATRET_1 RBM_FA1
#define RBM_DOUBLERET_1 RBM_FA1

// The registers trashed by the CORINFO_HELP_STOP_FOR_GC helper
#define RBM_STOP_FOR_GC_TRASH RBM_CALLEE_TRASH
Expand All @@ -239,8 +236,8 @@

#define REG_ARG_FIRST REG_A0
#define REG_ARG_LAST REG_A7
#define REG_ARG_FP_FIRST REG_F10
#define REG_ARG_FP_LAST REG_F17
#define REG_ARG_FP_FIRST REG_FA0
#define REG_ARG_FP_LAST REG_FA7
#define INIT_ARG_STACK_SLOT 0 // No outgoing reserved stack slots

#define REG_ARG_0 REG_A0
Expand All @@ -264,26 +261,8 @@
#define RBM_ARG_6 RBM_A6
#define RBM_ARG_7 RBM_A7

#define REG_FLTARG_0 REG_F10
#define REG_FLTARG_1 REG_F11
#define REG_FLTARG_2 REG_F12
#define REG_FLTARG_3 REG_F13
#define REG_FLTARG_4 REG_F14
#define REG_FLTARG_5 REG_F15
#define REG_FLTARG_6 REG_F16
#define REG_FLTARG_7 REG_F17

#define RBM_FLTARG_0 RBM_F10
#define RBM_FLTARG_1 RBM_F11
#define RBM_FLTARG_2 RBM_F12
#define RBM_FLTARG_3 RBM_F13
#define RBM_FLTARG_4 RBM_F14
#define RBM_FLTARG_5 RBM_F15
#define RBM_FLTARG_6 RBM_F16
#define RBM_FLTARG_7 RBM_F17

#define RBM_ARG_REGS (RBM_ARG_0|RBM_ARG_1|RBM_ARG_2|RBM_ARG_3|RBM_ARG_4|RBM_ARG_5|RBM_ARG_6|RBM_ARG_7)
#define RBM_FLTARG_REGS (RBM_FLTARG_0|RBM_FLTARG_1|RBM_FLTARG_2|RBM_FLTARG_3|RBM_FLTARG_4|RBM_FLTARG_5|RBM_FLTARG_6|RBM_FLTARG_7)
#define RBM_ARG_REGS (RBM_A0|RBM_A1|RBM_A2|RBM_A3|RBM_A4|RBM_A5|RBM_A6|RBM_A7)
#define RBM_FLTARG_REGS (RBM_FA0|RBM_FA1|RBM_FA2|RBM_FA3|RBM_FA4|RBM_FA5|RBM_FA6|RBM_FA7)

extern const regNumber fltArgRegs [MAX_FLOAT_REG_ARG];
extern const regMaskTP fltArgMasks[MAX_FLOAT_REG_ARG];
Expand Down
10 changes: 5 additions & 5 deletions src/coreclr/jit/unwindriscv64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ short Compiler::mapRegNumToDwarfReg(regNumber reg)

// On RISC-V registers from R0 to F31
// can be mapped directly to dwarf structure
if (reg >= REG_R0 && reg <= REG_F31)
if (reg >= REG_INT_FIRST && reg <= REG_FP_LAST)
{
dwarfReg = static_cast<short>(reg);
}
Expand Down Expand Up @@ -189,10 +189,10 @@ void Compiler::unwindSaveReg(regNumber reg, int offset)
else
{
// save_freg: 1101110x | xxxxzzzz | zzzzzzzz : save reg f(8 + #X) at [sp + #Z * 8], offset <= 2047
assert(REG_F8 == reg || REG_F9 == reg || // first legal register: F8
(REG_F18 <= reg && reg <= REG_F27)); // last legal register: F27
assert(REG_FS0 == reg || REG_FS1 == reg || // first legal register: FS0
(REG_FS2 <= reg && reg <= REG_FS11)); // last legal register: FS11

BYTE x = (BYTE)(reg - REG_F8);
BYTE x = (BYTE)(reg - REG_FS0);
assert(0 <= x && x <= 0x13);
assert(0 <= z && z <= 0xFFF);

Expand Down Expand Up @@ -597,7 +597,7 @@ void DumpUnwindInfo(Compiler* comp,
z = ((DWORD)(b2 & 0xF) << 8) | (DWORD)b3;

printf(" %02X %02X %02X save_freg X#%u Z#%u (0x%02X); fsd %s, [sp, #%u]\n", b1, b2, b3, x, z, z,
getRegName(REG_F8 + x), z * 8);
getRegName(REG_FS0 + x), z * 8);
}
#if 0
else if (b1 == 0xDE)
Expand Down

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