[libspike] add “disable vsew > vlmul * ELEN check” patch

nix/patches/spike/0001-enforce-lanewise-order-for-unordered-reduce.patch

@@ -1,7 +1,7 @@
 From 0ad6da899c20df0ce6120bc4ebd32edf01bdcd36 Mon Sep 17 00:00:00 2001
 From: SharzyL <[email protected]>
 Date: Sun, 25 Feb 2024 01:28:18 +0800
-Subject: [PATCH 1/2] enforce lanewise order for unordered reduce
+Subject: [PATCH 1/3] enforce lanewise order for unordered reduce
 
 ---
  riscv/insns/vfredusum_vs.h |  2 +-

nix/patches/spike/0002-disable-NaN-normalization.patch

@@ -1,7 +1,7 @@
 From 09a503dc94382798a1ee2f23b4b6894a12bc8207 Mon Sep 17 00:00:00 2001
 From: SharzyL <[email protected]>
 Date: Mon, 26 Aug 2024 20:08:47 +0800
-Subject: [PATCH 2/2] disable NaN normalization
+Subject: [PATCH 2/3] disable NaN normalization
 
 ---
  riscv/v_ext_macros.h | 6 +++---

nix/patches/spike/0003-disable-vsew-vlmul-ELEN-check.patch

@@ -0,0 +1,24 @@
+From 11789822d3cb6a493fe05e13dadac92d5830212d Mon Sep 17 00:00:00 2001
+From: SharzyL <[email protected]>
+Date: Tue, 3 Sep 2024 15:33:33 +0800
+Subject: [PATCH 3/3] disable 'vsew > vlmul * ELEN' check
+
+---
+ riscv/vector_unit.cc | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/riscv/vector_unit.cc b/riscv/vector_unit.cc
+index 08adc616..3a6ff15d 100644
+--- a/riscv/vector_unit.cc
++++ b/riscv/vector_unit.cc
+@@ -39,7 +39,6 @@ reg_t vectorUnit_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t new
+     vma = extract64(newType, 7, 1);
+
+     vill = !(vflmul >= 0.125 && vflmul <= 8)
+-           || vsew > std::min(vflmul, 1.0f) * ELEN
+            || (newType >> 8) != 0;
+
+     if (vill) {
+-- 
+2.43.0
+