Fix incorrect comment in ScalaDoc #1756
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| @@ -127,7 +127,7 @@ object RegNext { | |||
| * val x = Wire(UInt()) | |||
| * val y = Wire(UInt(8.W)) | |||
| * val r1 = RegInit(x) // width will be inferred | |||
| * val r2 = RegInit(y) // width is set to 8 | |||
| * val r2 = RegInit(y) // width will be inferred | |||
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Isn't it set to 8 eventually? What's the mechanism?
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inference in FIRRTL
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Can we add it as a comment? It may not be obvious that it is inferred, especially if the example code doesn't assign anything else to r2 that could change its width.
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@edwardcwang Here's the scastie demo. I am not sure of the mechanism, but it confirms, I believe, the correctness of Jack's change
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Read the whole ScalaDoc, that’s sort of the point of this whole example: https://www.chisel-lang.org/api/3.4.1/chisel3/RegInit$.html
It’s just that that particular comment is wrong and contradicts the correct info above.
jackkoenig
added
the
Please Merge
(cherry picked from commit d0db0b8)
(cherry picked from commit d0db0b8)
(cherry picked from commit d0db0b8)
(cherry picked from commit d0db0b8) Co-authored-by: Jack Koenig <[email protected]>
(cherry picked from commit d0db0b8) Co-authored-by: Jack Koenig <[email protected]>
(cherry picked from commit d0db0b8) Co-authored-by: Jack Koenig <[email protected]>
Contributor Checklist
docs/src?Type of Improvement
API Impact
No impact
Backend Code Generation Impact
No impact
Desired Merge Strategy
Release Notes
Fix incorrect example in ScalaDoc for width behavior of RegInit
Reviewer Checklist (only modified by reviewer)
Please Merge?