Fix incorrect comment in ScalaDoc (#1756)

(cherry picked from commit d0db0b8)
chipsalliance · Jan 27, 2021 · f4f4a5b · f4f4a5b
1 parent 1c851df
commit f4f4a5b
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/core/src/main/scala/chisel3/Reg.scala b/core/src/main/scala/chisel3/Reg.scala
@@ -127,7 +127,7 @@ object RegNext {
   * val x = Wire(UInt())
   * val y = Wire(UInt(8.W))
   * val r1 = RegInit(x) // width will be inferred
-  * val r2 = RegInit(y) // width is set to 8
+  * val r2 = RegInit(y) // width will be inferred
   * }}}
   *
   * 3. [[Aggregate]] initializer - width will be set to match the aggregate