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Replace hard asserts with assert macros with different behavior.
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@Rot127
Rot127 committed Sep 11, 2024
1 parent 73a647a commit cd0ed90
Showing 1 changed file with 20 additions and 19 deletions.
39 changes: 20 additions & 19 deletions llvm/utils/TableGen/PrinterCapstone.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1326,7 +1326,7 @@ void PrinterCapstone::decoderEmitterEmitPredicateFunction(
if (!Predicates.empty()) {
OS.indent(Indentation) << "switch (Idx) {\n";
OS.indent(Indentation)
<< "default: /* llvm_unreachable(\"Invalid index!\"); */\n";
<< "default: CS_ASSERT_RET_VAL(0 && \"Invalid index!\", false);\n";
unsigned Index = 0;
for (const auto &Predicate : Predicates) {
OS.indent(Indentation) << "case " << Index++ << ":\n";
Expand All @@ -1335,7 +1335,7 @@ void PrinterCapstone::decoderEmitterEmitPredicateFunction(
OS.indent(Indentation) << "}\n";
} else {
// No case statement to emit
OS.indent(Indentation) << "/* llvm_unreachable(\"Invalid index!\"); */\n";
OS.indent(Indentation) << "CS_ASSERT_RET_VAL(0 && \"Invalid index!\", false);\n";
}
Indentation -= 2;
OS.indent(Indentation) << "}\n\n";
Expand All @@ -1357,7 +1357,7 @@ void PrinterCapstone::decoderEmitterEmitDecoderFunction(
OS.indent(Indentation) << "InsnType tmp; \\\n";
OS.indent(Indentation) << "switch (Idx) { \\\n";
OS.indent(Indentation)
<< "default: /* llvm_unreachable(\"Invalid index!\"); */ \\\n";
<< "default: CS_ASSERT_RET_VAL(0 && \"Invalid index!\", MCDisassembler_Fail); \\\n";
unsigned Index = 0;
for (const auto &Decoder : Decoders) {
OS.indent(Indentation) << "case " << Index++ << ": \\\n";
Expand All @@ -1371,6 +1371,7 @@ void PrinterCapstone::decoderEmitterEmitDecoderFunction(

void PrinterCapstone::decoderEmitterEmitIncludes() const {
OS << "#include \"../../MCInst.h\"\n"
<< "#include \"../../cs_priv.h\"\n"
<< "#include \"../../LEB128.h\"\n\n";
}

Expand All @@ -1385,7 +1386,7 @@ void PrinterCapstone::decoderEmitterEmitSourceFileHeader() const {
void PrinterCapstone::asmWriterEmitSourceFileHeader(RecordKeeper &Records) const {
emitDefaultSourceFileHeader(OS);
OS << "#include <capstone/platform.h>\n"
<< "#include <assert.h>\n\n";
<< "#include \"../../cs_priv.h\"\n\n";
}

void PrinterCapstone::asmWriterEmitGetMnemonic(
Expand Down Expand Up @@ -1481,7 +1482,7 @@ void PrinterCapstone::asmWriterEmitPrintInstruction(

OS << " uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32)
<< "_t Bits = MnemonicInfo.second;\n"
<< " assert(Bits != 0 && \"Cannot print this instruction.\");\n";
<< " CS_ASSERT_RET(Bits != 0 && \"Cannot print this instruction.\");\n";

// Output the table driven operand information.
BitsLeft = OpcodeInfoBits - AsmStrBits;
Expand Down Expand Up @@ -1509,7 +1510,7 @@ void PrinterCapstone::asmWriterEmitPrintInstruction(
} else {
OS << " switch ((Bits >> " << (OpcodeInfoBits - BitsLeft) << ") & "
<< ((1 << NumBits) - 1) << ") {\n"
<< " default: assert(0 && \"Invalid command number.\");\n";
<< " default: CS_ASSERT_RET(0 && \"Invalid command number.\");\n";

// Print out all the cases.
for (unsigned J = 0, F = Commands.size(); J != F; ++J) {
Expand Down Expand Up @@ -1545,7 +1546,7 @@ void PrinterCapstone::asmWriterEmitOpCases(

void PrinterCapstone::asmWriterEmitInstrSwitch() const {
OS << " switch (MCInst_getOpcode(MI)) {\n";
OS << " default: assert(0 && \"Unexpected opcode.\");\n";
OS << " default: CS_ASSERT_RET(0 && \"Unexpected opcode.\");\n";
}

void PrinterCapstone::asmWriterEmitCompoundClosure(unsigned Indent,
Expand Down Expand Up @@ -1578,7 +1579,7 @@ void PrinterCapstone::asmWriterEmitInstruction(
// If this is the operand that varies between all of the instructions,
// emit a switch for just this operand now.
OS << " switch (MCInst_getOpcode(MI)) {\n";
OS << " default: assert(0 && \"Unexpected opcode.\");\n";
OS << " default: CS_ASSERT_RET(0 && \"Unexpected opcode.\");\n";
std::vector<std::pair<std::string, AsmWriterOperand>> OpsToPrint;
OpsToPrint.push_back(
std::make_pair(FirstInst.CGI->Namespace.str() + "_" +
Expand Down Expand Up @@ -1615,8 +1616,8 @@ void PrinterCapstone::asmWriterEmitGetRegNameAssert(
else
OS << "getRegisterName(unsigned RegNo) {\n";
OS << "#ifndef CAPSTONE_DIET\n";
OS << " assert(RegNo && RegNo < " << (RegSize + 1)
<< " && \"Invalid register number!\");\n"
OS << " CS_ASSERT_RET_VAL(RegNo && RegNo < " << (RegSize + 1)
<< " && \"Invalid register number!\", NULL);\n"
<< "\n";
}

Expand Down Expand Up @@ -1647,18 +1648,18 @@ void PrinterCapstone::asmWriterEmitAltIdxSwitch(
StringRef const &Namespace) const {
if (HasAltNames) {
OS << " switch(AltIdx) {\n"
<< " default: assert(0 && \"Invalid register alt name "
"index!\");\n";
<< " default: CS_ASSERT_RET_VAL(0 && \"Invalid register alt name "
"index!\", NULL);\n";
for (const Record *R : AltNameIndices) {
StringRef const AltName = R->getName();
OS << " case ";
if (!Namespace.empty())
OS << Namespace << "_";
OS << AltName << ":\n";
if (R->isValueUnset("FallbackRegAltNameIndex"))
OS << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
OS << " CS_ASSERT_RET_VAL(*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
<< "[RegNo-1]) &&\n"
<< " \"Invalid alt name index for register!\");\n";
<< " \"Invalid alt name index for register!\", NULL);\n";
else {
OS << " if (!*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
<< "[RegNo-1]))\n"
Expand All @@ -1672,8 +1673,8 @@ void PrinterCapstone::asmWriterEmitAltIdxSwitch(
}
OS << " }\n";
} else {
OS << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
<< " \"Invalid alt name index for register!\");\n"
OS << " CS_ASSERT_RET_VAL(*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
<< " \"Invalid alt name index for register!\", NULL);\n"
<< " return AsmStrs+RegAsmOffset[RegNo-1];\n";
}
OS << "#else\n"
Expand Down Expand Up @@ -1872,11 +1873,11 @@ void PrinterCapstone::asmWriterEmitPrintAliasOp(
<< " SStream *OS) {\n"
<< "#ifndef CAPSTONE_DIET\n";
if (PrintMethods.empty())
OS << " assert(0 && \"Unknown PrintMethod kind\");\n";
OS << " CS_ASSERT_RET(0 && \"Unknown PrintMethod kind\");\n";
else {
OS << " switch (PrintMethodIdx) {\n"
<< " default:\n"
<< " assert(0 && \"Unknown PrintMethod kind\");\n"
<< " CS_ASSERT_RET(0 && \"Unknown PrintMethod kind\");\n"
<< " break;\n";

for (unsigned I = 0; I < PrintMethods.size(); ++I) {
Expand All @@ -1903,7 +1904,7 @@ void PrinterCapstone::asmWriterEmitPrintMC(
<< " unsigned PredicateIndex) {\n"
<< " switch (PredicateIndex) {\n"
<< " default:\n"
<< " assert(0 && \"Unknown MCOperandPredicate kind\");\n"
<< " CS_ASSERT_RET_VAL(0 && \"Unknown MCOperandPredicate kind\", false);\n"
<< " return false;\n";

for (unsigned I = 0; I < MCOpPredicates.size(); ++I) {
Expand Down

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