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Fix: Src operand is not the out operand
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Rot127 committed Sep 7, 2024
1 parent 65a9134 commit 73a647a
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64InstrFormats.td
Original file line number Diff line number Diff line change
Expand Up @@ -11785,7 +11785,7 @@ class BaseCASEncoding<dag oops, dag iops, string asm, string operands,
class BaseCAS<string order, string size, RegisterClass RC>
: BaseCASEncoding<(outs RC:$out),(ins RC:$Rs, RC:$Rt, GPR64sp:$Rn),
"cas" # order # size, "\t$Rs, $Rt, [$Rn]",
"$out = $Rs",[]>,
"$out = $Rn",[]>,
Sched<[WriteAtomic]> {
let NP = 1;
}
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