Implement memories with sequential reads

[rachitnigam]

Fixes #165. We should make at least one frontend use these memories. Eventually, this will make it easier for us to use UltraRAM memories on FPGAs instead of BRAMs.

We can design a parameterized memory which takes read and write latencies as parameters. However, we don't currently have a way to specify the @static behavior of such memories because they are parameteric

[sampsyo]

Nice, looks great! It's not important for now, obviously, but it would be interesting to know what kind of FPGA memory Vivado (for example) automatically infers for this exact array+register combo.

About the comment re. frontend support… it occurs to me that we would in general like to make it as easy as possible for frontends to switch between different styles of memories. It obviously requires some code generation to abstract over different memory latencies and interfaces, but it would be interesting to think more about anything we could do to make this convenient. Maybe some creative high-level interface coupled with a lowering pass could help, for instance. Could be a fun topic for discussion!

[rachitnigam]

About the comment re. frontend support… it occurs to me that we would in general like to make it as easy as possible for frontends to switch between different styles of memories

Right! I think that would be important especially if we want to expose the same interface for BRAMs and UltraRAMs. I think the simple read_en/read_done combo would be a straightforward way to start but we'd need some reasoning to think about the logical to physical mapping (i.e., turning a logical memory into a BRAM or URAM) and adding static annotations for them.

This might also be interesting to @andrewb1999

[rachitnigam]

Added a test for these memories. Next step is updating the Dahlia frontend to generate non-combinational memories