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Adds some example railcom feedback #552

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merged 56 commits into from
Aug 2, 2021
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81787a8
Adds implementation for computing and checking CRC-8 according to the…
balazsracz Jul 4, 2021
d15598f
Fix style
balazsracz Jul 4, 2021
1be193b
Switches the DCC decoder to use zero-copy buffering.
balazsracz Jul 3, 2021
e1908f7
Adds yield when the next packet shows up.
balazsracz Jul 3, 2021
d875dda
Fix style to be simpler to read.
balazsracz Jul 4, 2021
b97b1dd
Fixes bugs around packet length.
balazsracz Jul 4, 2021
0402f64
Merge branch 'bracz-crc8-d-m' into bracz-dccdecode-ec
balazsracz Jul 4, 2021
1ccb6a2
Adds code to verify the XOR and the CRC8 checksum.
balazsracz Jul 4, 2021
6919811
Up max payload.
balazsracz Jul 4, 2021
c1ff8e2
Adds a delta capability for tuning the railcom cutout timing.
balazsracz Jul 4, 2021
1d9c161
Prints the correct expected DLC in case of an error.
balazsracz Jul 4, 2021
dabbe85
Prints the correct expected DLC in case of an error.
balazsracz Jul 4, 2021
6a0e928
Merge branch 'bracz-dccdecode-ec' into merge-branch
balazsracz Jul 4, 2021
d331e97
Adds support for the STM32UART to set the buad rate via ioctl.
balazsracz Jul 3, 2021
67cb4b7
Merge branch 'bracz-st-uart-baud' into merge-branch
balazsracz Jul 4, 2021
1d35dc8
Adds a railcom UART transmitter to the f091 dcc decoder.
balazsracz Jul 3, 2021
c2c3c2a
Merge branch 'merge-branch' into bracz-st-decoder-update
balazsracz Jul 4, 2021
dd460f0
Adds support for F0 command decoding.
balazsracz Jul 4, 2021
57e600e
Fix bug and unnecessary copy.
balazsracz Jul 10, 2021
a15f12b
Adds documentation to explain where the test vector comes from.
balazsracz Jul 10, 2021
059e837
Merge commit 'd551997cd9ef47ac5edb709272c4e7f1f29f677f' into bracz-cr…
balazsracz Jul 10, 2021
b54137a
Merge branch 'master' into bracz-dccdecoder-zero-copy
balazsracz Jul 10, 2021
8c6a449
Merge branch 'bracz-crc8-d-m' into bracz-dcc-ec-base
balazsracz Jul 10, 2021
b75b422
Merge branch 'bracz-dccdecoder-zero-copy' into bracz-dcc-ec-base
balazsracz Jul 10, 2021
736a621
Merge branch 'bracz-dcc-ec-base' into bracz-dccdecode-ec
balazsracz Jul 10, 2021
3662805
Fix whitespace.
balazsracz Jul 10, 2021
2ad111d
Merge branch 'master' into bracz-st-uart-baud
balazsracz Jul 10, 2021
eacf704
Merge commit '57b05968a67ff385ad6b6353d7744aa20da7763c' into bracz-dc…
balazsracz Jul 10, 2021
aa29ab9
Merge branch 'bracz-dccdecode-ec' into merge-branch
balazsracz Jul 10, 2021
95dbd74
Merge branch 'bracz-st-uart-baud' into merge-branch
balazsracz Jul 10, 2021
deef2a3
Merge branch 'merge-branch' into bracz-st-decoder-update
balazsracz Jul 10, 2021
a2e5d3d
Fixes up the compilation of the Tiva DCC decoder target.
balazsracz Jul 10, 2021
074da45
Adds API for railcom sender implementation.
balazsracz Jul 10, 2021
4fff459
Adds railcom sender implementation for STM32.
balazsracz Jul 10, 2021
8e2ae77
Merge branch 'dcc-railcom-send' into bracz-st-decoder-update
balazsracz Jul 10, 2021
83885ef
Adds a call in the DCC interrupt to fill in the railcom feedback.
balazsracz Jul 10, 2021
a31291a
Adds the send functions to the railcom driver.
balazsracz Jul 10, 2021
9340f69
Switches uart1 to the stm32 railcom driver.
balazsracz Jul 10, 2021
ef99a1f
Fixes bugs in the stm32 railcom sender.
balazsracz Jul 10, 2021
99e5ea4
Implements the railcom sender in the main for the dcc-decoder app.
balazsracz Jul 10, 2021
b27c448
Fixes bugs in the stm32 railcom sender.
balazsracz Jul 10, 2021
faee0ce
Merge branch 'dcc-railcom-send' into bracz-st-decoder-update
balazsracz Jul 10, 2021
7d83805
Adds a call in the DCC interrupt to fill in the railcom feedback.
balazsracz Jul 10, 2021
0e812a8
Adds the send functions to the railcom driver.
balazsracz Jul 10, 2021
ce00406
Fixes bugs in the stm32 railcom sender.
balazsracz Jul 10, 2021
7250973
Merge commit 'ce00406ba1fe40cf1002f787e0338eaa8ed49231' into bracz-st…
balazsracz Jul 11, 2021
8ea1264
Removes unneeded forward declaration.
balazsracz Jul 11, 2021
0e96d33
Merge branch 'dcc-railcom-send' into bracz-st-decoder-update
balazsracz Jul 11, 2021
7820fe0
Sends all zeros to check timing.
balazsracz Jul 11, 2021
310f849
Adds routines to encode railcom data for a sender.
balazsracz Jul 11, 2021
ee2f0d2
Merge branch 'bracz-railcom-encode' into bracz-st-decoder-update
balazsracz Jul 11, 2021
6c430b6
Fix comment.
balazsracz Aug 2, 2021
0c781dc
Merge branch 'master' into dcc-railcom-send
balazsracz Aug 2, 2021
7074024
Merge branch 'dcc-railcom-send' into bracz-st-decoder-update
balazsracz Aug 2, 2021
55e0f93
Merge branch 'master' into bracz-railcom-encode
balazsracz Aug 2, 2021
a1d1b8e
Merge branch 'bracz-railcom-encode' into bracz-st-decoder-update
balazsracz Aug 2, 2021
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104 changes: 103 additions & 1 deletion applications/dcc_decoder/main.cxx
Original file line number Diff line number Diff line change
Expand Up @@ -41,12 +41,102 @@
#include "dcc/DccDebug.hxx"
#include "utils/constants.hxx"
#include "utils/StringPrintf.hxx"
#include "dcc/PacketProcessor.hxx"
#include "dcc/RailCom.hxx"
#include "freertos_drivers/common/RailcomDriver.hxx"
#include "freertos/tc_ioctl.h"

#include "hardware.hxx"

Executor<1> executor("executor", 0, 2048);

// We reserve a lot of buffer for transmit to cover for small hiccups in the
// host reading data.
OVERRIDE_CONST(serial_tx_buffer_size, 2048);
OVERRIDE_CONST(main_thread_priority, 3);

// The DCC address to listen at. This is in wire format. The first address byte
// is the high byte.
static const uint16_t dcc_address_wire = 3 << 8;

uint8_t f0 = 0;

void process_packet(const DCCPacket& p) {
if (p.packet_header.csum_error) {
return;
}
if (p.dlc < 3) {
return;
}
if (p.payload[0] != (dcc_address_wire >> 8)) {
return;
}
unsigned ofs = 1;
if ((dcc_address_wire >> 8) > 127) {
// Two byte address.
ofs++;
if (p.payload[1] != (dcc_address_wire & 0xff)) {
return;
}
}
if ((p.payload[ofs] >> 5) == 0b100)
{
// F0-F4 packet
ofs++;
f0 = p.payload[ofs] & 0b00010000 ? 1 : 0;
}
}

class IrqProcessor : public dcc::PacketProcessor {
public:
IrqProcessor() {
}

/// Called in the main to prepare the railcom feedback packets.
void init()
{
ch1_.reset(0);
ch1_.add_ch1_data(0x00);
ch1_.add_ch1_data(0x00);

ch2_.reset(0);
ch2_.add_ch2_data(0);
ch2_.add_ch2_data(0);
ch2_.add_ch2_data(0);
ch2_.add_ch2_data(0);
ch2_.add_ch2_data(0);
ch2_.add_ch2_data(0);
#if 0
ch2_.add_ch2_data(dcc::RailcomDefs::ACK);
ch2_.add_ch2_data(dcc::RailcomDefs::ACK);
ch2_.add_ch2_data(dcc::RailcomDefs::ACK);
ch2_.add_ch2_data(dcc::RailcomDefs::ACK);
ch2_.add_ch2_data(dcc::RailcomDefs::ACK);
ch2_.add_ch2_data(dcc::RailcomDefs::ACK);
#endif
}

void packet_arrived(
const DCCPacket *pkt, RailcomDriver *railcom) override {
DEBUG1_Pin::set(true);
if (pkt->packet_header.csum_error) {
return;
}
ch1_.feedbackKey = pkt->feedback_key;
ch2_.feedbackKey = pkt->feedback_key;
railcom->send_ch1(&ch1_);
railcom->send_ch2(&ch2_);
DEBUG1_Pin::set(false);
}

private:
dcc::Feedback ch1_;
dcc::Feedback ch2_;
} irqProc;

extern "C" {
void set_dcc_interrupt_processor(dcc::PacketProcessor *p);
}

/** Entry point to application.
* @param argc number of command line arguments
Expand All @@ -61,12 +151,22 @@ int appl_main(int argc, char *argv[])
//int wfd = ::open("/dev/serUSB0", O_RDWR);
int wfd = ::open("/dev/ser0", O_RDWR);
HASSERT(wfd >= 0);
int rcfd = ::open("/dev/ser1", O_WRONLY);
HASSERT(rcfd >= 0);
auto ret = ::ioctl(rcfd, TCBAUDRATE, 250000);
HASSERT(ret == 0);

irqProc.init();
set_dcc_interrupt_processor(&irqProc);

int cnt = 0;
while (1)
{
DCCPacket packet_data;
int sret = ::read(fd, &packet_data, sizeof(packet_data));
HASSERT(sret == sizeof(packet_data));
DEBUG1_Pin::set(true);
process_packet(packet_data);
long long t = os_get_time_monotonic();
string txt = StringPrintf("\n%02d.%06d %04d ",
(unsigned)((t / 1000000000) % 100),
Expand All @@ -78,7 +178,9 @@ int appl_main(int argc, char *argv[])
// not enough space in the serial write buffer, we need to throw away
// data.
++cnt;
resetblink((cnt >> 3) & 1);
uint8_t blink = ((cnt >> 3) & 15) == 1u ? 1 : 0;
resetblink(f0 ^ blink);
DEBUG1_Pin::set(false);
}
return 0;
}
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,7 @@
#include "Stm32Uart.hxx"
#include "Stm32Can.hxx"
#include "Stm32EEPROMEmulation.hxx"
#include "Stm32RailcomSender.hxx"
#include "hardware.hxx"
#include "DummyGPIO.hxx"

Expand All @@ -73,6 +74,9 @@ const char *STDERR_DEVICE = "/dev/ser0";
/** UART 0 serial driver instance */
static Stm32Uart uart0("/dev/ser0", USART2, USART2_IRQn);

/** RailCom sender UART */
static Stm32RailcomSender railcomUart("/dev/ser1", USART1, USART1_IRQn);

/** CAN 0 CAN driver instance */
static Stm32Can can0("/dev/can0");

Expand Down Expand Up @@ -125,13 +129,13 @@ struct DccDecoderHW
/// How many usec later/earlier should the railcom cutout start happen.
static int time_delta_railcom_pre_usec()
{
return 0;
return 80 - 26;
}

/// How many usec later/earlier should the railcom cutout middle happen.
static int time_delta_railcom_mid_usec()
{
return 0;
return 193 - 185;
}

/// How many usec later/earlier should the railcom cutout end happen.
Expand Down Expand Up @@ -160,14 +164,16 @@ struct DccDecoderHW
static constexpr auto OS_IRQn = TSC_IRQn;
};

// Dummy implementation because we are not a railcom detector.
NoRailcomDriver railcom_driver;

Stm32DccDecoder<DccDecoderHW> dcc_decoder0(
"/dev/dcc_decoder0", &railcom_driver);
"/dev/dcc_decoder0", &railcomUart);

extern "C" {

void set_dcc_interrupt_processor(dcc::PacketProcessor *p)
{
dcc_decoder0.set_packet_processor(p);
}

/** Blink LED */
uint32_t blinker_pattern = 0;
static uint32_t rest_pattern = 0;
Expand Down Expand Up @@ -274,6 +280,7 @@ void hw_preinit(void)
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_USART1_CLK_ENABLE();
__HAL_RCC_USART2_CLK_ENABLE();
__HAL_RCC_CAN1_CLK_ENABLE();
__HAL_RCC_TIM14_CLK_ENABLE();
Expand All @@ -293,6 +300,14 @@ void hw_preinit(void)
gpio_init.Pin = GPIO_PIN_3;
HAL_GPIO_Init(GPIOA, &gpio_init);

/* USART1 pinmux on railCom TX pin PB6 */
gpio_init.Mode = GPIO_MODE_AF_PP;
gpio_init.Pull = GPIO_PULLUP;
gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
gpio_init.Alternate = GPIO_AF0_USART1;
gpio_init.Pin = GPIO_PIN_6;
HAL_GPIO_Init(GPIOB, &gpio_init);

/* CAN pinmux on PB8 and PB9 */
gpio_init.Mode = GPIO_MODE_AF_PP;
gpio_init.Pull = GPIO_PULLUP;
Expand Down Expand Up @@ -339,6 +354,7 @@ void timer3_interrupt_handler(void) {

void touch_interrupt_handler(void) {
dcc_decoder0.os_interrupt_handler();
portYIELD_FROM_ISR(true);
}

}
Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,18 @@ GPIO_PIN(LED_GREEN_RAW, LedPin, A, 5);
GPIO_PIN(SW_USER, GpioInputPU, C, 13);

GPIO_PIN(DCC_IN, GpioInputPU, A, 6);
GPIO_PIN(RAILCOM_TX, GpioOutputSafeHigh, B, 6);

typedef GpioInitializer<LED_GREEN_RAW_Pin, SW_USER_Pin, DCC_IN_Pin> GpioInit;
GPIO_PIN(DEBUG1, GpioOutputSafeLow, C, 9);
GPIO_PIN(DEBUG2, GpioOutputSafeLow, C, 8);

typedef GpioInitializer< //
LED_GREEN_RAW_Pin, //
SW_USER_Pin, //
DCC_IN_Pin, //
DEBUG1_Pin, //
DEBUG2_Pin>
GpioInit;

typedef LED_GREEN_RAW_Pin BLINKER_RAW_Pin;
typedef BLINKER_Pin LED_GREEN_Pin;