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Add AD4052-ARDZ project #1504

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common: coraz7s: Add IIC for Arduino SCL SDA
Add AXI IIC Controller connected to Arduino SCL SDA ports.
Generally, to read the EVB EEPROM.

Signed-off-by: Jorge Marques <[email protected]>
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gastmaier committed Dec 3, 2024
commit c1b92249971428fd35be83ef9be7f8701b2848a8
11 changes: 9 additions & 2 deletions projects/common/coraz7s/coraz7s_system_bd.tcl
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

@@ -8,6 +8,7 @@

create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_ard

create_bd_port -dir O spi0_csn_2_o
create_bd_port -dir O spi0_csn_1_o
@@ -59,6 +60,10 @@ ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
ad_ip_instance proc_sys_reset sys_dma_rstgen
ad_ip_parameter sys_dma_rstgen CONFIG.C_EXT_RST_WIDTH 1

# iic (arduino sda/scl)

ad_ip_instance axi_iic axi_iic_ard

# system reset/clock definitions

ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
@@ -92,6 +97,7 @@ ad_connect gpio_i sys_ps7/GPIO_I
ad_connect gpio_o sys_ps7/GPIO_O
ad_connect gpio_t sys_ps7/GPIO_T
ad_connect fixed_io sys_ps7/FIXED_IO
ad_connect iic_ard axi_iic_ard/iic

# spi connections

@@ -131,7 +137,7 @@ ad_connect sys_concat_intc/In15 GND
ad_connect sys_concat_intc/In14 GND
ad_connect sys_concat_intc/In13 GND
ad_connect sys_concat_intc/In12 GND
ad_connect sys_concat_intc/In11 GND
ad_connect sys_concat_intc/In11 axi_iic_ard/iic2intc_irpt
ad_connect sys_concat_intc/In10 GND
ad_connect sys_concat_intc/In9 GND
ad_connect sys_concat_intc/In8 GND
@@ -146,4 +152,5 @@ ad_connect sys_concat_intc/In0 GND

# interconnects and address mapping

ad_cpu_interconnect 0x41600000 axi_iic_ard
ad_cpu_interconnect 0x45000000 axi_sysid_0
6 changes: 5 additions & 1 deletion projects/common/coraz7s/coraz7s_system_constr.xdc
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

@@ -16,3 +16,7 @@ set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports led[3]]
set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports led[4]] ; ## LED1_R
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports led[5]] ; ## LED1_G

# iic

set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports iic_ard_scl] ; ## Arduino_SCL
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports iic_ard_sda] ; ## Arduino_SDA
11 changes: 8 additions & 3 deletions projects/common/coraz7s/system_top.v
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -61,7 +61,10 @@ module system_top (
inout fixed_io_ps_srstb,

inout [ 1:0] btn,
inout [ 5:0] led
inout [ 5:0] led,

inout iic_ard_scl,
inout iic_ard_sda
);

// internal signals
@@ -135,6 +138,8 @@ module system_top (
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o());
.spi1_sdo_o (),
.iic_ard_scl_io (iic_ard_scl),
.iic_ard_sda_io (iic_ard_sda));

endmodule