AIE/Design/04-Cust-PFM-EMU: update to 2022.1 (#205)

* Updating blacklist to blocklist and whitelist to allowlist in description.json * Updating version TO 2022.1 * Updating README * Updated link stage generated file to .xsa instead of .xclbin for 2022 Co-authored-by: virata <[email protected]>
Xilinx · Apr 4, 2022 · f259343 · f259343
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diff --git a/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/README.md b/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/README.md
@@ -9,7 +9,7 @@
 
 # Custom Platform Emulation with RTL Kernel
 
-***Version: Vitis 2021.2***
+***Version: Vitis 2022.1***
 
 ## Introduction
 
@@ -164,7 +164,7 @@ Because there is no HLS kernel in the ADF graph, the `system.cfg` file, which is
 3. Build the emulation design using the following command:
 
     ```bash
-    v++ -l --platform ../../../Versal_Platform_Creation/Tutorial-VCK190_Custom/ref_files/step3_pfm/platform_repo/vck190_custom/export/vck190_custom/vck190_custom.xpfm s2mm.xo mm2s.xo polar_clip.xo libadf.a -t hw_emu --save-temps -g --config system.cfg -o tutorial.xclbin
+    v++ -l --platform ../../../Versal_Platform_Creation/Tutorial-VCK190_Custom/ref_files/step3_pfm/platform_repo/vck190_custom/export/vck190_custom/vck190_custom.xpfm s2mm.xo mm2s.xo polar_clip.xo libadf.a -t hw_emu --save-temps -g --config system.cfg -o tutorial.xsa
     ```
 
     or
@@ -216,7 +216,7 @@ v++ -p -t hw_emu \
     --package.boot_mode=sd \
     --package.kernel_image=../../../../Versal_Platform_Creation/Tutorial-VCK190_Custom/ref_files/step2_petalinux/build/petalinux/images/linux/Image \
     --package.defer_aie_run \
-    --package.sd_file host.exe ../tutorial.xclbin ../libadf.a
+    --package.sd_file host.exe ../tutorial.xsa ../libadf.a
 cd ..
 ```
 

diff --git a/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/description.json b/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/description.json
@@ -3,8 +3,8 @@
     "description": "04-custome-platform-emulation",
     "flow": "versal",
 
-    "platform_whitelist": [ "vck190"],
-    "platform_blacklist": [],
+    "platform_allowlist": [ "vck190"],
+    "platform_blocklist": [],
 
     "testinfo": {
         "disable": false,

diff --git a/AI_Engine_Development/Feature_Tutorials/12-axis-traffic-generator/README.md b/AI_Engine_Development/Feature_Tutorials/12-axis-traffic-generator/README.md
@@ -1,6 +1,6 @@
 <table>
  <tr>
-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>2021.2 Versal® AI Engine</h1>
+   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>2022.1 Versal® AI Engine</h1>
    </td>
  </tr>
  <tr>
@@ -117,28 +117,24 @@ To run through this tutorial, you will need to download and install the followin
 
 When the elements of the Vitis&trade; software platform are installed, update the target platform environment script.
 
-Create a script file named `env_setup_2021.sh` in your favorite text editor. Replace the placeholders with the appropriate paths:
+Create a script file named `env_setup_2022.sh` in your favorite text editor. Replace the placeholders with the appropriate paths:
 
 ```bash
 export DSPLIB_ROOT=<YOUR-DSPLIB-DIRECTORY>
 export PLATFORM_REPO_PATHS=<YOUR-PLATFORM-DIRECTORY>
 
-source <XILINX-INSTALL-LOCATION>/Vitis/2021.2/settings64.sh
+source <XILINX-INSTALL-LOCATION>/Vitis/2022.1/settings64.sh
 ```
 
 Then source the environment script:
 
 ```bash
-source env_setup_2021.sh
-```  
+source env_setup_2022.sh
+```
 
 ## *Validation*: Confirming Tool Installation
 
-Ensure that you are using the 2021.2 version of Xilinx&reg; tools.
-
-### *Validation*: Confirming Tool Installation
-
-Ensure that you are using the 2021.1 version of Xilinx&reg; tools.
+Ensure that you are using the 2022.1 version of Xilinx&reg; tools.
 
 ```bash
 which vitis
@@ -188,7 +184,7 @@ In the previous figure the AXIS traffic generator provides a path to the AI Engi
     PLIO_WIDTH := 64
     KERNEL_XO := pl_kernels/sim_ipc_axis_master_${PLIO_WIDTH}.xo pl_kernels/sim_ipc_axis_slave_${PLIO_WIDTH}.xo
     ...
-    VPP_LINK_FLAGS := -l --platform $(BASE_PLATFORM) $(KERNEL_XO) $(GRAPH_O) -t $(TARGET) --save-temps -g --config $(CONFIG_FILE) -o $(PFM).xclbin
+    VPP_LINK_FLAGS := -l --platform $(BASE_PLATFORM) $(KERNEL_XO) $(GRAPH_O) -t $(TARGET) --save-temps -g --config $(CONFIG_FILE) -o $(PFM).xsa
     ```
 
 ### Understanding Python
@@ -417,7 +413,6 @@ For `ai_engine_0` the names are provided in the `graph.cpp` when instantiating a
 
 You can see the `v++` switches in more detail in the [Vitis Unified Software Platform Documentation](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021.2/ug1393-vitis-application-acceleration.pdf).
 
-You can see the `v++` switches in more detail in the [Vitis Unified Software Platform Documentation](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug1393-vitis-application-acceleration.pdf).
 
 To build the design, run the following command:
 

diff --git a/AI_Engine_Development/Feature_Tutorials/12-axis-traffic-generator/description.json b/AI_Engine_Development/Feature_Tutorials/12-axis-traffic-generator/description.json
@@ -3,8 +3,8 @@
     "description": "12-axis-traffic-generator",
     "flow": "versal",
 
-    "platform_whitelist": [ "vck190"],
-    "platform_blacklist": [],
+    "platform_allowlist": [ "vck190"],
+    "platform_blocklist": [],
 
     "testinfo": {
         "disable": true,