test request (#101)

* Updated targets for Spirite testing * Updated targets for Sprite * added host, xclbin, and emconfig targets * updated with new options * updated with latest options * Added default STEP * updated path to OpenCV * added tasks {} to enable setup of OpenCV environment * backed out taks{} * added task{} to setup OpenCV environment * added --platform to KRNL_COMPILE_OPTS * copied name to description removed blacklist platform * restored missing files * copied name to description removed blacklist * copied name to description removed blacklist * copied name to description removed blacklist * copied description to name removed blacklist * copied name to decription removed blacklist * copied name to description removed blacklist * copied name to description added U50 to whitelist removed blacklist * copied name to description removed blacklist * copied name to description removed blacklist * copied name to description removed blacklist * copied name to description removed blacklist * copied name to description removed blacklist * copied name to description removed blacklist * copied description to name removed blacklist * added host, xclbin, emconfig build targets * added host, xclbin, and emconfig as make targets * added host, xclbin, emconfig as make targets * added host, xclbin, emconfig as make targets * removed PREBUILT updated hardware build instructions * disabled PREBUILT * Update lab3_build_app_kernel.md * Create user.xml * added user-xml for user-managed * changed HOST=user to default * commented ip2 and ip3 * changed memory bank to 1 * added multi_params.json * Create multi_params.json * added multi_params.json * added multi_params.json * Added for Sprite Enable * added --platform to xo and xclbin * Update README.md * update to 2021.2 * update for 2021.2 * update for 2021.2 * update for 2021.2 * Update synth_and_analysis.md * Update synth_and_analysis.md * added Pipeline II error * Add files via upload
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diff --git a/Getting_Started/Vitis_HLS/README.md b/Getting_Started/Vitis_HLS/README.md
@@ -36,26 +36,26 @@ Vitis High-Level Synthesis (HLS) is a key part of the Vitis application accelera
 
 > **TIP:** Vitis HLS can also be used to generate Vivado IP from C/C++ code, but that flow is not the subject of this tutorial. Although similar, there are some significant differences between producing Vitis XO kernels and Vivado RTL IP. However, you can use this tutorial as a general introduction to the Vitis HLS tool. 
 
-In this tutorial, you will work through the Vitis HLS tool GUI to build, analyze, and optimize a hardware kernel. You are working through the Vitis kernel flow in the Vitis tool. For more information, refer to [Enabling the Vitis Kernel Flow](https://www.xilinx.com/cgi-bin/docs/rdoc?v=2021.1;t=vitis+doc;d=vitis_hls_process.html;a=uiy1584905571731) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
+In this tutorial, you will work through the Vitis HLS tool GUI to build, analyze, and optimize a hardware kernel. You are working through the Vitis kernel flow in the Vitis tool. For more information, refer to [Enabling the Vitis Kernel Flow](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Vitis-HLS-Process-Overview) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
 
 ### Before You Begin
 
 The labs in this tutorial use:
 
 * BASH Linux shell commands.
-* 2021.1 Vitis core development kit release and the *xilinx_u200_gen3x16_xdma_1_202110_1* platform. If necessary, it can be easily ported to other versions and platforms.
+* 2021.2 Vitis core development kit release and the *xilinx_u200_gen3x16_xdma_1_202110_1* platform. If necessary, it can be easily ported to other versions and platforms.
 
 >**IMPORTANT:**  
 >
-> * Before running any of the examples, make sure you have installed the Vitis core development kit as described in [Installation](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/acceleration_installation.html#vhc1571429852245) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).
+> * Before running any of the examples, make sure you have installed the Vitis core development kit as described in [Installation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installation-Requirements) in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).
 >* If you run applications on the Xilinx® Alveo™ Data Center accelerator cards, ensure the card and software drivers have been correctly installed by following the instructions To complete installation, follow the instructions on the [Alveo Product Documentation tab](https://www.xilinx.com/products/boards-and-kits/alveo.html).
 
 ### Setup the environment to run Vitis
 
 To configure the environment to run Vitis, run the following scripts which set up the environment to run in a specific command shell.
 
 ```bash
-source <Vitis_install_path>/Vitis/2021.1/settings64.sh
+source <Vitis_install_path>/Vitis/2021.2/settings64.sh
 source /opt/xilinx/xrt/setup.sh
 ```
 

diff --git a/Getting_Started/Vitis_HLS/dataflow_design.md b/Getting_Started/Vitis_HLS/dataflow_design.md
@@ -1,6 +1,6 @@
 <table class="sphinxhide">
  <tr>
-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>2021.1 Vitis™ Application Acceleration Tutorials</h1>
+   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>2021.2 Vitis™ Application Acceleration Tutorials</h1>
    <a href="https://github.com/Xilinx/Vitis-Tutorials/tree/2020.1">See 2020.2 Tutorials</a>
   </td>
  </tr>
@@ -28,13 +28,13 @@
 
 ### 4. Reviewing the DATAFLOW Optimization
 
-In the earlier steps, you found different ways to optimize the DCT algortithm so that you could achieve an II=1 with the pipelined loops. In this step, you use the DATAFLOW directive to enable task-level parallelism for functions or loops. For more information, refer to [set_directive_dataflow](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/optdirectives.html#rdd1585343102486) in the Vitis HLS flow of the Vitis Unified Software Platform documentation (UG1416).
+In the earlier steps, you found different ways to optimize the DCT algortithm so that you could achieve an II=1 with the pipelined loops. In this step, you use the DATAFLOW directive to enable task-level parallelism for functions or loops. For more information, refer to [set_directive_dataflow](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/set_directive_dataflow) in the Vitis HLS flow of the Vitis Unified Software Platform documentation (UG1416).
 
 The DATAFLOW optimization tries to create task-level parallelism between the various functions in the code on top of the loop-level parallelism where possible.
 
 #### Create a New Solution
 
-As described in [Creating Additional Solutions](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/optimizinghlsproject.html#wmt1584281647955) in the Vitis HLS flow of the Vitis Unified Software Platform documentation (UG1416), you can create multiple solutions to let you pursue or explore different approaches to optimizing your design. Here you will create a new solution to explore the use of the DATAFLOW optimization.
+As described in [Creating Additional Solutions](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Creating-Additional-Solutions) in the Vitis HLS flow of the Vitis Unified Software Platform documentation (UG1416), you can create multiple solutions to let you pursue or explore different approaches to optimizing your design. Here you will create a new solution to explore the use of the DATAFLOW optimization.
 
 1. In the Explorer view, select the top-level project (`dct_prj`).
 2. Right-click and select **New Solution**.
@@ -80,7 +80,7 @@ As described in [Creating Additional Solutions](https://www.xilinx.com/html_docs
 
 #### View the Dataflow Graph
 
-Vitis HLS also provides a Dataflow Graph viewer as one of the features in the Analysis perspective. The DATAFLOW optimization is a dynamic optimization that can only really be understood after C/RTL co-simulation which provides needed performance data. After synthesis, you must run co-simulation. For more information, refer to [C/RTL Co-Simulation in Vitis HLS](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/cosimulationinvitishls.html) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
+Vitis HLS also provides a Dataflow Graph viewer as one of the features in the Analysis perspective. The DATAFLOW optimization is a dynamic optimization that can only really be understood after C/RTL co-simulation which provides needed performance data. After synthesis, you must run co-simulation. For more information, refer to [C/RTL Co-Simulation in Vitis HLS](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/C/RTL-Co-Simulation-in-Vitis-HLS) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
 
 1. From the menu select **Solution > Run C/RTL Co-Simulation**.
    The Co-simulation dialog box displays.
@@ -96,7 +96,7 @@ Vitis HLS also provides a Dataflow Graph viewer as one of the features in the An
 
    >**TIP:** You can tell if the design has a Dataflow graph by the presence of the ![Dataflow Icon](./images/icon_dataflow.png) icon.
 
-   The DataFlow Viewer displays the function and the flow through the function. After running C/RTL co-simulation, the elements of the graph are filled out with performance data, and the Process and Channel tables beneath the graph are also filled out. Without the performance data provided by co-simulation, the graph and tables will have NA values to reflect the missing values. For more information, refer to [Dataflow Viewer](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/analyzingresultssynthesis.html#twx1584322463297) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
+   The DataFlow Viewer displays the function and the flow through the function. After running C/RTL co-simulation, the elements of the graph are filled out with performance data, and the Process and Channel tables beneath the graph are also filled out. Without the performance data provided by co-simulation, the graph and tables will have NA values to reflect the missing values. For more information, refer to [Dataflow Viewer](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Dataflow-Viewer) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
 
    ![Dataflow Graph](./images/dataflow_graph_channels.png)
 

diff --git a/Getting_Started/Vitis_HLS/images/bind_storage-ram2p.png b/Getting_Started/Vitis_HLS/images/bind_storage-ram2p.png
diff --git a/Getting_Started/Vitis_HLS/images/config_compile.png b/Getting_Started/Vitis_HLS/images/config_compile.png
diff --git a/Getting_Started/Vitis_HLS/images/create_project-default_perspective.png b/Getting_Started/Vitis_HLS/images/create_project-default_perspective.png
diff --git a/Getting_Started/Vitis_HLS/images/dct_synthesis_report-array_partition.png b/Getting_Started/Vitis_HLS/images/dct_synthesis_report-array_partition.png
diff --git a/Getting_Started/Vitis_HLS/images/dct_synthesis_report.png b/Getting_Started/Vitis_HLS/images/dct_synthesis_report.png
diff --git a/Getting_Started/Vitis_HLS/images/pipeline-6.png b/Getting_Started/Vitis_HLS/images/pipeline-6.png
diff --git a/Getting_Started/Vitis_HLS/images/pipeline-defined-ii.png b/Getting_Started/Vitis_HLS/images/pipeline-defined-ii.png
diff --git a/Getting_Started/Vitis_HLS/images/pipeline-pragma.png b/Getting_Started/Vitis_HLS/images/pipeline-pragma.png
diff --git a/Getting_Started/Vitis_HLS/images/run_c_synthesis.png b/Getting_Started/Vitis_HLS/images/run_c_synthesis.png
diff --git a/Getting_Started/Vitis_HLS/new_project.md b/Getting_Started/Vitis_HLS/new_project.md
@@ -1,6 +1,6 @@
 <table class="sphinxhide">
  <tr>
-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>2021.1 Vitis™ Application Acceleration Tutorials</h1>
+   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>2021.2 Vitis™ Application Acceleration Tutorials</h1>
    <a href="https://github.com/Xilinx/Vitis-Tutorials/tree/2020.2">See 2020.2 Tutorials</a>
   </td>
  </tr>
@@ -65,7 +65,7 @@ In this tutorial, you are working with a simple discrete cosine transform (DCT)
 
          The Add/Remove Testbench Files page of the New Project wizard displays.
 
-         Writing a good testbench can greatly increase your productivity because C functions execute in orders of magnitude faster than RTL simulations. Using C to develop and validate the algorithm before synthesis is much faster than developing and debugging RTL code. For more information, refer to [Writing a Testbench](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/verifyingcodecsimulation.html#sav1584759936384) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
+         Writing a good testbench can greatly increase your productivity because C functions execute in orders of magnitude faster than RTL simulations. Using C to develop and validate the algorithm before synthesis is much faster than developing and debugging RTL code. For more information, refer to [Writing a Testbench](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Writing-a-Test-Bench) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
 
       ![Add Sources](./images/create_project-add_testbench.png)
 
@@ -85,7 +85,7 @@ In this tutorial, you are working with a simple discrete cosine transform (DCT)
 6. Make the following selections:
       1. Specify the **Solution Name**, or use the default name. 
       2. Specify the **Period** for the clock as the default period of 10 ns.
-      3. Leave the clock uncertainty blank. The default clock uncertainty, when it is not specified, is 27% of the clock period. For more information, refer to [Specifying the Clock Frequency](https://www.xilinx.com/cgi-bin/docs/rdoc?v=2021.1;t=vitis+doc;d=creatingnewvitishlsproject.html;a=ycw1585572210561) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
+      3. Leave the clock uncertainty blank. The default clock uncertainty, when it is not specified, is 27% of the clock period. For more information, refer to [Specifying the Clock Frequency](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Specifying-the-Clock-Frequency) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
       4. Define the part for the project by selecting the **Browse (...)** command.
 
             This opens the Device Selection dialog box (our device shows in the **Boards** category, see next step...).
@@ -103,7 +103,7 @@ In this tutorial, you are working with a simple discrete cosine transform (DCT)
 
 8. In the Solution Configuration dialog box, select the **Vitis Kernel Flow Target** from the dropdown menu.
 
-   This enables the creation of a Vitis application acceleration hardware kernel (.xo) as an output for the project. For more information on how enabling the Vitis kernel flow configures the default behavior of the tool, refer to [Vitis HLS Process Overview](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/vitis_hls_process.html#djn1584047476918) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
+   This enables the creation of a Vitis application acceleration hardware kernel (.xo) as an output for the project. For more information on how enabling the Vitis kernel flow configures the default behavior of the tool, refer to [Vitis HLS Process Overview](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Vitis-HLS-Process-Overview) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
 
 9. With your project settings now configured, click **Finish**.
     Vitis HLS opens the new project in the default view.

diff --git a/Getting_Started/Vitis_HLS/optimization_techniques.md b/Getting_Started/Vitis_HLS/optimization_techniques.md
@@ -1,6 +1,6 @@
 <table class="sphinxhide">
  <tr>
-   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>2021.1 Vitis™ Application Acceleration Tutorials</h1>
+   <td align="center"><img src="https://www.xilinx.com/content/dam/xilinx/imgs/press/media-kits/corporate/xilinx-logo.png" width="30%"/><h1>2021.2 Vitis™ Application Acceleration Tutorials</h1>
    <a href="https://github.com/Xilinx/Vitis-Tutorials/tree/2020.1">See 2020.2 Tutorials</a>
   </td>
  </tr>
@@ -64,7 +64,7 @@ In the last section, the **config_compile** command is a tool configuration comm
     With the Source Code Editor open, the right hand of the IDE also displays the Outline and Directive views for your code.
 
     * **Outline view**: Displays an outline of the displayed source code file. Select a region or function for quick navigation of the code.
-    * **Directives view**: Select operations or elements of your code to assign `HLS pragmas` to your source code, or to assign `set_directive` commands to a Tcl script that is associated with the active solution. For more information, refer to [Adding Pragmas and Directives](https://www.xilinx.com/cgi-bin/docs/rdoc?v=2021.1;t=vitis+doc;d=optimizinghlsproject.html;a=gip1583519972576) in the Vitis HLS FLow of the Vitis Unified Software Platform Documentation (UG1416).
+    * **Directives view**: Select operations or elements of your code to assign `HLS pragmas` to your source code, or to assign `set_directive` commands to a Tcl script that is associated with the active solution. For more information, refer to [Adding Pragmas and Directives](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Adding-Pragmas-and-Directives) in the Vitis HLS FLow of the Vitis Unified Software Platform Documentation (UG1416).
 
 2. In the Directives view, right-click the `dct_2d` function, and select **Insert Directive**.
 
@@ -88,7 +88,7 @@ The `HLS PIPELINE II=4` is added to the Directive view.
 
 7. Click **C Synthesis** to rerun synthesis.
 
-    Notice the Interval column for the `dct_2d` function reads 4, but it is not reported as a problem.
+    Notice the Interval column for the `dct_2d` function does not meet the II requirement and is reported as a problem.
 
     ![Pipeline Defined II](./images/pipeline-defined-ii.png)
 
@@ -100,7 +100,7 @@ The `HLS PIPELINE II=4` is added to the Directive view.
 
 In some designs, a Guidance message `Unable to schedule load operation...` indicates a load/load (or read/read conflict) issue with memory transactions. In these cases rather than accepting the latency, you could try to optimize the implementation to achieve the best performance (II=1).
 
-The specific problem of reading or writing to memory can possibly be addressed by increasing the available memory ports to read from, or to write to. One approach is to use the BIND_STORAGE pragma or directive to specify the type of device resource to use in implementing the storage. BIND_STORAGE defines a specific device resource for use in implementing a storage structure associated with a variable in the RTL. For more information, refer to [BIND_STORAGE](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/hls_pragmas.html#chr1584844747152) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
+The specific problem of reading or writing to memory can possibly be addressed by increasing the available memory ports to read from, or to write to. One approach is to use the BIND_STORAGE pragma or directive to specify the type of device resource to use in implementing the storage. BIND_STORAGE defines a specific device resource for use in implementing a storage structure associated with a variable in the RTL. For more information, refer to [BIND_STORAGE](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-bind_storage) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
 
  ![BIND_STORAGE](./images/bind_storage_pragma.png)
 
@@ -132,7 +132,7 @@ The specific problem of reading or writing to memory can possibly be addressed b
 
 Another approach to solve memory port conflicts is to use the ARRAY_PARTITION directive to reconfigure the structure of an array. ARRAY_PARTITION lets you partition an array into smaller arrays or into individual registers instead of one large array. This effectively either increases the amount of read and write ports for the storage and potentially improves the throughput of the design. 
 
-However, ARRAY_PARTITION also requires more memory instances or registers, and so increases area and resource consumption. For more information, refer to [ARRAY_PARTITION](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/hls_pragmas.html#gle1504034361378) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416). If partitioning large arrays, this can also increase the compile time.
+However, ARRAY_PARTITION also requires more memory instances or registers, and so increases area and resource consumption. For more information, refer to [ARRAY_PARTITION](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-array_partition) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416). If partitioning large arrays, this can also increase the compile time.
 
 1. In the Directives view, select the array variables, **col_inbuf** and **buf_2d_out**  from the associated II violations.
 

diff --git a/Getting_Started/Vitis_HLS/reference-files/Makefile b/Getting_Started/Vitis_HLS/reference-files/Makefile
@@ -40,9 +40,9 @@ xclbin: $(XO) $(XCLBIN)
 
 # Building kernel
 $(XO): ./src/dct.cpp
-	v++ $(KRNL_COMPILE_OPTS) -c -k dct -I'$(<D)' -o'$@' '$<'
+	v++ $(KRNL_COMPILE_OPTS) -c --platform $(PLATFORM) -k dct -I'$(<D)' -o'$@' '$<'
 $(XCLBIN): $(XO)
-	v++ $(KRNL_LINK_OPTS) -l -o'$@' $(+)
+	v++ $(KRNL_LINK_OPTS) -l --platform $(PLATFORM) -o'$@' $(+)
 
 # Building Host
 $(HOST_EXE): ./src/dct_top.cpp