ESP32 revisions to support esp32-c3 and s2 variants #2365

mikee47 · 2021-09-15T08:53:46Z

This PR improves support for ESP32 soc variants with testing on real hardware:

ESP32 devkit V1 (ESP-WROOM32)
AI-thinker esp-c3-32s
AI-thinker esp-12k (esp32-s2) devkits

SDK build changes

SDK builds automatically if files or config changed. Ninja is very fast so low overhead.

Create separate SDK project for debug/release builds.
Use separate build directory for Esp32 variants, i.e. {SMING_ARCH}/{ESP_VARIANT}.
Esp8266 & Host unchanged.

Build only selected SDK components: reduces number of files to compile by about 1/3rd.

Remove unused components, including VFS an SDK_FULL_BUILD option.

Move SDK build targets into appropriate help categories

Remove redundant sdk-defconfig target

Fixes

Fix interrupts() function to work with RISCV.
system_os_post() must be in IRAM.
Fix building for esp32c3 with DISABLE_WIFI=1.

Flashing

Fix flashing for esp32c3 & esp32s2 variants, variant must be passed to esptool.

Fix issues with mismatched types, e.g. RISCV compiler for esp32c3 uses different type definitions.

Route _write_r to m_nputs and set IDF logging function to m_vprintf

Rework uart driver using IDF HAL

Works reliably with esp32-s2 and c3
UART default pin allocations selected by variant
Peripheral registers are mapped in two places on s2 (see tech. manual), need to use AHB_FIFO mappings.
Use HAL to accommodate these differences.
Ensure internal memory used for serial buffer
Remove uartHardware structure, located in flash: use GetDriver which is OK for use in ISR.
Register ISR to be called in interrupt context so it remains active whilst flash is disabled.

Enable GDB panic handler

Can now use regular make gdb if panic occurs.

Esp32 Framework changes

Remove redundant network code

Fix flashmem_get_address() for all Esp32 variants

Fix PROGMEM definition

Only applies to DROM, not IROM so simplify `isFlashPtr` also

Implement CPU frequency setting

A bit more involved on the ESP32, requires power management to be enabled via SDK.

HostTests changes

Simplify initorder test

Compile HttpRequest, TcpClient test modules only for Host

Fix heap checking for shared pointers

Move XorOutputStream from Network Component into gen. pop. - not particularly network-centric.
Allows test code to compile with

Clock tests sometimes generate interrupt WDT timeout on ESP32: don't leave interrupts disabled whilst printing to UART.

Ensures that switching between build types uses correct settings.

Remove unused components Disable VFS (not used by Sming)

e.g. RISCV compiler for esp32c3 uses different type definitions

…ntf`

State `0` doesn't work for esp32s2, so use more appropriate function

Not particularly network-centric

…ch SMING_ARCH value

Works reliably with esp32-s2 and c3 UART default pin allocations selected by variant Peripheral registers are mapped in two places on s2 (see tech. manual), need to use AHB_FIFO mappings. Use HAL to accommodate these differences. Ensure internal memory used for serial buffer Remove `uartHardware` structure, located in flash: use `GetDriver` which is OK for use in ISR. Register ISR to be called in interrupt context so it remains active whilst flash is disabled.

Don't leave interrupts disabled whilst printing to UART

Only applies to DROM, not IROM so simplify `isFlashPtr` also

A bit more involved on the ESP32, requires power management to be enabled via SDK.

Further features can be reintroduced carefully as required.

slaff · 2021-09-15T14:13:58Z

Sming/Arch/Esp32/Components/driver/uart.cpp

@@ -314,11 +329,10 @@ static void IRAM_ATTR uart_isr(smg_uart_instance_t* inst)
 	}

 	auto uart = inst->uart;
-	auto uart_nr = uart->uart_nr;
-	auto& hw = uartHardware[uart_nr];
+	auto dev = getDevice(uart->uart_nr);


I am getting segfaults pointing to this line. Steps to reproduce:

Use ESP-WROOM-32 chip

Compile the Basic_Wifi sample with the following command:

make SMING_ARCH=Esp32 DEBUG_VERBOSE_LEVEL=3

Flash the applications.

I am getting always the following error:

(terminal output)

Sming. Let's do smart things! Re-enable cpu cache. Guru Meditation Error: Core 1 panic'ed (LoadProhibited). Exception was unhandled. Core 1 register dump: PC : 0x40086c1b PS : 0x00060031 A0 : 0x40081dc4 A1 : 0x3ffb0ba0 A2 : 0x3ffb53f4 A3 : 0x3ffcef94 A4 : 0x00000002 A5 : 0x00000000 A6 : 0x0000000a A7 : 0x3ffb0ba0 A8 : 0x80086c18 A9 : 0x3ffb0b80 A10 : 0xbad00bad A11 : 0x00000000 A12 : 0x00000000 A13 : 0x3ffb4b20 A14 : 0xffffffff A15 : 0x00000004 SAR : 0x00000000 EXCCAUSE: 0x0000001c EXCVADDR: 0xbad00bb5 LBEG : 0x00000000 LEND : 0x00000000 LCOUNT : 0x00000000 Backtrace:0x40086c18:0x3ffb0ba0 0x40081dc1:0x3ffb0c50 0x4008265c:0x3ffbad80 0x400842fc:0x3ffbada0 ELF file SHA256: b4a6e9970b27af4c Entering gdb stub now.

(gdb output)

Remote debugging using /dev/ttyUSB0 0x40086c1b in uart_isr (inst=0x3ffb53f4 <uartInstances>) at /opt/Sming/Sming/Arch/Esp32/Components/driver/uart.cpp:332 332 auto dev = getDevice(uart->uart_nr);

And decoded stacktrace:

0x40086c18:0x3ffb0ba0 0x40081dc1:0x3ffb0c50 0x4008265c:0x3ffbad80 0x400842fc:0x3ffbada0 0x40086c18: uart_isr(smg_uart_instance_t*) at /opt/Sming/Sming/Arch/Esp32/Components/driver/uart.cpp:335 0x40081dc1: _xt_lowint1 at /opt/esp-idf-4.3/components/freertos/port/xtensa/xtensa_vectors.S:1105 0x4008265c: spi_flash_op_block_func at /opt/esp-idf-4.3/components/spi_flash/cache_utils.c:115 (discriminator 1) 0x400842fc: ipc_task at /opt/esp-idf-4.3/components/esp_ipc/ipc.c:62

Can you try to reproduce the problem? At least for me the same sample works just fine with the current develop.

I get the same problem... It can be fixed by reverting line 462 using ESP_INTR_FLAG_LOWMED instead of ESP_INTR_FLAG_IRAM. But that's a hack.

Turns out the real reason is the compiler puts switch tables in flash, even for IRAM_ATTR code blocks. Using if statements and the problem goes away. Lesson learned.

Turns out the real reason is the compiler puts switch tables in flash, even for IRAM_ATTR code blocks. Using if statements and the problem goes away. Lesson learned.

Wow! Thanks for the fix and the explanation.

For info., just re-tested the esp32-c3 & esp32-s2 and neither have a problem, however both still put the switch table in flash.

Retested with ESP-WROOM-32 and works as expected. Thank you @mikee47 .

Turns out the real reason is the compiler puts switch tables in flash

I seem to remember that at some point with the old ESP8266 compilers vtables could placed in a desired location (GCC compiler recompilation required.). And this brought to my attention the fact that also jump tables could be taken care of. GCC has an option for the placement of jump tables. Take a look at
https://gcc.gnu.org/onlinedocs/gcc/Code-Gen-Options.html and search for option -fno-jump-tables. Unfortunately, as far as I know, it is not possible to instruct the compiler to not use jump tables for switch statements in IRAM code blocks only.

Looks like switch statements are to be avoided inside IRAM_ATTR code.

This PR improves support for ESP32 soc variants with testing on real hardware: - ESP32 devkit V1 (ESP-WROOM32) - AI-thinker `esp-c3-32s` - AI-thinker `esp-12k` (esp32-s2) devkits **SDK build changes** SDK builds automatically if files or config changed. Ninja is very fast so low overhead. Create separate SDK project for debug/release builds. Use separate build directory for Esp32 variants, i.e. `{SMING_ARCH}/{ESP_VARIANT}`. Esp8266 & Host unchanged. Build only selected SDK components: reduces number of files to compile by about 1/3rd. Remove unused components, including VFS an SDK_FULL_BUILD option. Move SDK build targets into appropriate help categories Remove redundant `sdk-defconfig` target **Fixes** Fix `interrupts()` function to work with RISCV. `system_os_post()` must be in IRAM. Fix building for esp32c3 with DISABLE_WIFI=1. **Flashing** Fix flashing for esp32c3 & esp32s2 variants, variant must be passed to esptool. Fix issues with mismatched types, e.g. RISCV compiler for esp32c3 uses different type definitions. Route `_write_r` to `m_nputs` and set IDF logging function to `m_vprintf` **Rework uart driver using IDF HAL** Works reliably with esp32-s2 and c3 UART default pin allocations selected by variant Peripheral registers are mapped in two places on s2 (see tech. manual), need to use AHB_FIFO mappings. Use HAL to accommodate these differences. Ensure internal memory used for serial buffer Remove `uartHardware` structure, located in flash: use `GetDriver` which is OK for use in ISR. Register ISR to be called in interrupt context so it remains active whilst flash is disabled. **Enable GDB panic handler** Can now use regular `make gdb` if panic occurs. **Esp32 Framework changes** Remove redundant network code Fix `flashmem_get_address()` for all Esp32 variants Fix PROGMEM definition Only applies to DROM, not IROM so simplify `isFlashPtr` also Implement CPU frequency setting A bit more involved on the ESP32, requires power management to be enabled via SDK. **HostTests changes** Simplify `initorder` test Compile HttpRequest, TcpClient test modules only for Host Fix heap checking for shared pointers Move XorOutputStream from Network Component into gen. pop. - not particularly network-centric. Allows test code to compile with Clock tests sometimes generate interrupt WDT timeout on ESP32: don't leave interrupts disabled whilst printing to UART.

mikee47 added 25 commits September 11, 2021 21:06

Create separate SDK project for debug/release builds.

cdd9b20

Ensures that switching between build types uses correct settings.

Remove redundant sdk-defconfig target

43ff9b1

Doc fixes

eed59be

Build only selected SDK components

5ec3fec

Remove unused components Disable VFS (not used by Sming)

Move SDK build targets into appropriate help categories

3e35732

Fix issues with mismatched types

2336d5b

e.g. RISCV compiler for esp32c3 uses different type definitions

Fix flashing for esp32c3 & esp32s2 variants

3fd6553

Route _write_r to m_nputs and set IDF logging function to `m_vpri…

6c5a3d9

…ntf`

Simplify initorder test

a8f8c8b

Fix interrupts() function

8cbaa7f

State `0` doesn't work for esp32s2, so use more appropriate function

system_os_post() must be in IRAM

2716d22

Move XorOutputStream from Network Component into gen. pop.

fe10fb0

Not particularly network-centric

Compile HttpRequest, TcpClient test modules only for Host

115ef05

Remove redundant network code

7fef095

Fix building for esp32c3 with DISABLE_WIFI=1

fbf5f98

Use separate build directory for variants, persist ESP_VARIANT for ea…

109d5f5

…ch SMING_ARCH value

Enable GDB panic handler and fix serial debugging

6b7db65

SDK builds automatically if files or config changed

5df7adb

Clock tests sometimes generate interrupt WDT timeout on ESP32

45619a4

Don't leave interrupts disabled whilst printing to UART

Fix heap checking for shared pointers

1e6c932

Fix flashmem_get_address() for all Esp32 variants

798d87e

Fix PROGMEM definition

a2a9a46

Only applies to DROM, not IROM so simplify `isFlashPtr` also

Implement CPU frequency setting

400c1da

A bit more involved on the ESP32, requires power management to be enabled via SDK.

Remove SDK_FULL_BUILD option, strip out more unrequired definitions.

01a3a2f

Further features can be reintroduced carefully as required.

mikee47 changed the title ~~Feature/esp32c3s2~~ ESP32 revisions to support esp32-c3 and s2 variants Sep 15, 2021

slaff added this to the 4.4.0 milestone Sep 15, 2021

slaff added the 3 - Review label Sep 15, 2021

slaff reviewed Sep 15, 2021

View reviewed changes

Fix uart exception on ESP32-WROOM

7cf98e5

Looks like switch statements are to be avoided inside IRAM_ATTR code.

slaff removed the 3 - Review label Sep 16, 2021

slaff merged commit 3f63abb into SmingHub:develop Sep 16, 2021

slaff mentioned this pull request Sep 17, 2021

Preparation for Release 4.4.0 #2298

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ESP32 revisions to support esp32-c3 and s2 variants #2365

ESP32 revisions to support esp32-c3 and s2 variants #2365

mikee47 commented Sep 15, 2021

slaff Sep 15, 2021

mikee47 Sep 15, 2021

slaff Sep 15, 2021

mikee47 Sep 15, 2021

slaff Sep 16, 2021

slaff Sep 16, 2021

ESP32 revisions to support esp32-c3 and s2 variants #2365

ESP32 revisions to support esp32-c3 and s2 variants #2365

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