Skip to content

Commit

Permalink
ESP32 revisions to support esp32-c3 and s2 variants (#2365)
Browse files Browse the repository at this point in the history
This PR improves support for ESP32 soc variants with testing on real hardware:

- ESP32 devkit V1 (ESP-WROOM32)
- AI-thinker `esp-c3-32s`
- AI-thinker `esp-12k` (esp32-s2) devkits


**SDK build changes**

SDK builds automatically if files or config changed. Ninja is very fast so low overhead.

Create separate SDK project for debug/release builds.
Use separate build directory for Esp32 variants, i.e. `{SMING_ARCH}/{ESP_VARIANT}`.
Esp8266 & Host unchanged.

Build only selected SDK components: reduces number of files to compile by about 1/3rd.

Remove unused components, including VFS an SDK_FULL_BUILD option.

Move SDK build targets into appropriate help categories

Remove redundant `sdk-defconfig` target


**Fixes**

Fix `interrupts()` function to work with RISCV.
`system_os_post()` must be in IRAM.
Fix building for esp32c3 with DISABLE_WIFI=1.


**Flashing**

Fix flashing for esp32c3 & esp32s2 variants, variant must be passed to esptool.

Fix issues with mismatched types, e.g. RISCV compiler for esp32c3 uses different type definitions.

Route `_write_r` to `m_nputs` and set IDF logging function to `m_vprintf`


**Rework uart driver using IDF HAL**

Works reliably with esp32-s2 and c3
UART default pin allocations selected by variant
Peripheral registers are mapped in two places on s2 (see tech. manual), need to use AHB_FIFO mappings.
Use HAL to accommodate these differences.
Ensure internal memory used for serial buffer
Remove `uartHardware` structure, located in flash: use `GetDriver` which is OK for use in ISR.
Register ISR to be called in interrupt context so it remains active whilst flash is disabled.

**Enable GDB panic handler**

Can now use regular `make gdb` if panic occurs.


**Esp32 Framework changes**

Remove redundant network code

Fix `flashmem_get_address()` for all Esp32 variants

Fix PROGMEM definition

    Only applies to DROM, not IROM so simplify `isFlashPtr` also

Implement CPU frequency setting

    A bit more involved on the ESP32, requires power management to be enabled via SDK.


**HostTests changes**

Simplify `initorder` test

Compile HttpRequest, TcpClient test modules only for Host

Fix heap checking for shared pointers

Move XorOutputStream from Network Component into gen. pop. - not particularly network-centric.
Allows test code to compile with 

Clock tests sometimes generate interrupt WDT timeout on ESP32: don't leave interrupts disabled whilst printing to UART.
  • Loading branch information
mikee47 authored and slaff committed Sep 27, 2021
1 parent 7571b91 commit 19394b9
Show file tree
Hide file tree
Showing 50 changed files with 503 additions and 1,421 deletions.
6 changes: 5 additions & 1 deletion Sming/Arch/Esp32/Components/driver/include/driver/hw_timer.h
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@

#pragma once

#if defined(SUBARCH_ESP32) || defined(SUBARCH_ESP32S2)
#if defined(SUBARCH_ESP32)
#define FRC_TIMER_ENABLED
#endif

Expand Down Expand Up @@ -158,8 +158,12 @@ __forceinline uint32_t hw_timer1_read(void)
*
*************************************/

#ifdef FRC_TIMER_ENABLED
constexpr uint32_t HW_TIMER2_CLKDIV = TIMER_CLKDIV_1;
constexpr uint32_t HW_TIMER2_CLK = HW_TIMER_BASE_CLK >> HW_TIMER2_CLKDIV;
#else
constexpr uint32_t HW_TIMER2_CLK = 1000000;
#endif

/**
* @brief Read current timer2 value
Expand Down
Loading

0 comments on commit 19394b9

Please sign in to comment.