Add support for SoC Mercury XU5 on base board ST1 #67
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EmilioPeJu
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glennchid
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thomascobb
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I don't understand half of this PR, but as long as @glennchid understands it then the bits I know about look fine
Now it is possible to have folders hdl_zynq and hdl_zynqmp in folder common as well as in a module folder. The folder is optional and will not generate an error if it doesn't exist
In Zynq UltraScale+, some parameters are mandatory or have conflicting defaults. The default fifo implentation is common clock native, which does not support having a data count output. Another difference is that the 'asymetric port width' flag is needed when the input data width and the output data width don't match.
The extension server expects a function
It provides readings of on-board temperatures and voltages. The VHDL part is a dummy entity to make the server consider this block.
IDDR is not available in zynqmp, therefore a IDDRE1 must be used, which has a slightly different interface.
ODDR is not available in zynqmp, ODDRE1 is used instead.
Target implementations might prefer to specify only the fpga part and not the board part (which in most cases is not available)
ATF is required for platform zynqmp.
PMU firmware is mandatory and the PS system will not boot without it.
Zynq only requires FSBL and u-boot, while zynqmp requires FSBL, PMU firmware, arm trusted firmware and u-boot.
The pin number must be encoded as a string to simplify parsing, as the led_daemon is a shell script running in a limited environment.
Two apps were added: - xu5_st1-no-fmc: provides the standard soft blocks - xu5_st1-fmc_acq430: provides the standard soft blocks and support for D-TACQ ACQ430 FMC module There is one physical modification needed to use FMCs, given that the I2C connected to the FMC is not the same as the PS associated I2C, we need to join both from the base board connectors: - Connect pin 38 from Anios IO connector 0 to pin 38 from Anios IO Connector 1 - Connect pin 40 from Anios IO connector 0 to pin 40 from Anios IO Connector 1
EmilioPeJu
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Mar 15, 2024
At the moment only 2 targets defines it: PandABlocks: MAC from a qspi memory PAndABrick: MAC from a secure EEPROM This is part of a solution for issue #67
EmilioPeJu
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Mar 15, 2024
At the moment only 2 targets defines it: PandABlocks: MAC from a qspi memory PAndABrick: MAC from a secure EEPROM This is part of a solution for issue #67
EmilioPeJu
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that referenced
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Mar 15, 2024
At the moment only 2 targets define it: PandABlocks: MAC from a qspi memory PAndABrick: MAC from a secure EEPROM This is part of a solution for issue #67
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This was successfully tested on a ME-XU5-4EV-1I-D11E-G1 mounted on a ST1.