Merge branch 'master' into xu5-st1

common/hdl/reg_top.vhd

@@ -66,6 +66,7 @@ signal POS_READ_RST         : std_logic;
 signal POS_READ_RSTB        : std_logic;
 signal POS_READ_VALUE       : std_logic_vector(31 downto 0);
 signal POS_READ_CHANGES     : std_logic_vector(31 downto 0);
+signal FPGA_CAPABILITIES    : std_logic_vector(31 downto 0);
 
 signal read_address         : natural range 0 to (2**read_address_i'length - 1);
 signal write_address        : natural range 0 to (2**write_address_i'length - 1);
@@ -175,6 +176,10 @@ BIT_READ_RSTB <= '1' when (read_ack = '1' and
 POS_READ_RSTB <= '1' when (read_ack = '1' and
                  read_address = REG_POS_READ_VALUE) else '0';
 
+-- Register of FPGA capabilities 
+-- Bit0: presence of PCAP_STD_DEV functionality
+FPGA_CAPABILITIES <= (0 => PCAP_SUPPORTS_STD_DEV,
+                      others => '0');
 --------------------------------------------------------------------------
 -- Status Register Read
 --------------------------------------------------------------------------
@@ -194,6 +199,8 @@ begin
                 read_data_o <= POS_READ_VALUE;
             when REG_POS_READ_CHANGES =>
                 read_data_o <= POS_READ_CHANGES;
+            when REG_FPGA_CAPABILITIES =>
+                read_data_o <= FPGA_CAPABILITIES;
             when others =>
                 read_data_o <= (others => '0');
         end case;

common/python/generate_app.py

@@ -26,6 +26,10 @@
 ROOT = os.path.join(os.path.dirname(__file__), "..", "..")
 TEMPLATES = os.path.join(os.path.abspath(ROOT), "common", "templates")
 
+# List of allowing FPGA options enabled in target ini file
+VALID_FPGA_OPTIONS = [
+    "pcap_std_dev",
+]
 
 def jinja_context(**kwargs):
     context = dict(pad=pad)
@@ -60,6 +64,7 @@ def __init__(self, app, app_build_dir):
         self.fpga_blocks = []  # type: List[BlockConfig]
         self.server_blocks = []  # type: List[BlockConfig]
         self.target_sites = [] #type: List[TargetSiteConfig]
+        self.fpga_options = [] #type: List[]
         self.parse_ini_files(app)
         self.generate_config_dir()
         self.generate_wrappers()
@@ -105,6 +110,12 @@ def parse_ini_files(self, app):
                 siteType, siteInfo = target.split(':')
                 site=TargetSiteConfig(siteType, siteInfo)
                 self.target_sites.append(site)
+            # Read in which FPGA options are enabled on target
+            options = ini_get(target_ini, '.', 'options', '')
+            self.fpga_options = filter(None, [option.strip() for option in options.split(',')])
+            for fpga_option in self.fpga_options:
+                assert fpga_option in VALID_FPGA_OPTIONS, \
+                    "%r option defined in target ini file is not valid" % fpga_option
         # Implement the blocks for the soft blocks
         self.implement_blocks(app_ini, "modules", "soft")
 
@@ -273,6 +284,7 @@ def generate_soft_blocks(self):
         context = jinja_context(
             fpga_blocks=self.fpga_blocks,
             target_sites=self.target_sites,
+            fpga_options=self.fpga_options,
             carrier_bit_bus_length=carrier_bit_bus_length,
             carrier_pos_bus_length=carrier_pos_bus_length,
             total_bit_bus_length=total_bit_bus_length,

common/templates/registers_server

@@ -32,6 +32,9 @@
     PCAP_ARM                13
     PCAP_DISARM             14
 
+    # FPGA Capabilities Value
+    FPGA_CAPABILITIES       15
+
     # Range of MAC addresses
     MAC_ADDRESS_BASE        16 .. 23
 

common/templates/top_defines.vhd.jinja2

@@ -28,22 +28,25 @@ subtype MOD_RANGE               is natural range 0 to MOD_COUNT-1;
 constant RD_ADDR2ACK            : std_logic_vector(4 downto 0) := "00010";
 
 -- Block instantiation numbers--------------------------------------------
-constant ENC_NUM            : natural := 4;
+constant ENC_NUM                : natural := 4;
 --------------------------------------------------------------------------
 
 -- Bit Bus Width, Multiplexer Select Width -------------------------------
-constant BBUSW              : natural := 128;
-constant BBUSBW             : natural := 7;
+constant BBUSW                  : natural := 128;
+constant BBUSBW                 : natural := 7;
 
 -- Position Bus Width, Multiplexer Select Width.
-constant PBUSW              : natural := {{ total_pos_bus_length }};
-constant PBUSBW             : natural := 5;
+constant PBUSW                  : natural := {{ total_pos_bus_length }};
+constant PBUSBW                 : natural := 5;
 
 -- Extended Position Bus Width.
-constant EBUSW              : natural := 12;
+constant EBUSW                  : natural := 12;
 --------------------------------------------------------------------------
 
-constant DCARD_MONITOR      : std_logic_vector(2 downto 0) := "011";
+constant DCARD_MONITOR          : std_logic_vector(2 downto 0) := "011";
+
+-- Presence of PCAP_STD_DEV functionality
+constant PCAP_SUPPORTS_STD_DEV  : std_logic := '{{ ("pcap_std_dev" in fpga_options) | int}}';
 
 type t_mode_group is array (5 downto 0) of std_logic_vector(31 downto 0);
 type t_mode is array (PBUSW-1 downto 0) of t_mode_group;

tests/python/test_data/app-expected/config_d/registers

@@ -32,6 +32,9 @@
     PCAP_ARM                13
     PCAP_DISARM             14
 
+    # FPGA Capabilities Value
+    FPGA_CAPABILITIES       15
+
     # Range of MAC addresses
     MAC_ADDRESS_BASE        16 .. 23