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Installation
Some building blocks, such as MPF, include software that dynamically configures and interacts with the BBB hardware. The process for building and installing BBB software include files and libraries is nearly identical to the recipe for building and installing the OPAE SDK.
Start by cloning the BBB repository:
$ git clone https://github.com/OPAE/intel-fpga-bbb
Build the BBB libraries:
$ cd intel-fpga-bbb
$ mkdir mybuild
$ cd mybuild
$ cmake ..
$ make
$ make install
By default, the BBBs will be installed into /usr/local and integrated into the OPAE SDK trees. You can change this installation prefix from /usr/local into something else by adding -DCMAKE_INSTALL_PREFIX= to the cmake command above. In most cases, you should choose the same CMAKE_INSTALL_PREFIX for both the OPAE SDK and the BBBs.
Start by defining the environment variable FPGA_BBB_CCI_SRC with the full path of the intel-fpga-bbb directory created in the git clone step above. By convention, synthesis scripts import building blocks through this variable.
The hardware (hw) tree of each building block contains three directories: rtl, sim and par. Source code is in the rtl directory. The sim and par directories contain rules for important source and timing constraints into ASE (sim) and Quartus (par).
OPAE provides scripts for constructing synthesis and simulation compilation environments from a single source specification. These scripts, afu_synth_setup and afu_sim_setup, are described in the first step of the tutorial. Both scripts invoke another script, rtl_src_config, to build synthesis and simulator configuration files. Recent BBBs provide a file that can be included by AFU rtl_src_config source specifications. For example:
# Include MPF
C:${FPGA_BBB_CCI_SRC}/BBB_cci_mpf/hw/rtl/cci_mpf_sources.txt
BBBs also provide simulation and synthesis-specific source lists. Using these files is typically less convenient than the rtl_src_config method, but is functionally equivalent. The rtl_src_config specification is typically implemented by including these simulation and synthesis-specific source lists.
Use a relative include (-F) to import a building block's sources for simulation in ASE. For example:
# Include MPF
-F $FPGA_BBB_CCI_SRC/BBB_cci_mpf/hw/sim/cci_mpf_sim_addenda.txt
# Include clock crossing FIFO
-F $FPGA_BBB_CCI_SRC/BBB_ccip_async/hw/sim/ccip_async_sim_addenda.txt
Each building block provides a qsf file in hw/par that imports both sources and timing constraints into Quartus. Include these qsf files during synthesis, placement and routing phases. The mechanism is similar to the recommendation for simulation:
## Import MPF and async FIFO libraries
source $::env(FPGA_BBB_CCI_SRC)/BBB_cci_mpf/hw/par/qsf_cci_mpf_PAR_files.qsf
source $::env(FPGA_BBB_CCI_SRC)/BBB_ccip_async/hw/par/ccip_async_addenda.qsf