BBB_ccip_async

CCI-P Clock Crossing Shim

The clock crossing shim connects a pair of CCI-P interfaces together when the two interfaces are connected to different clocks. Individual dual clock FIFOs are instantiated for each direction of each CCI-P channel. The CCI-P soft reset signal is also mapped to the destination clock domain. FIFO buffer sizes are configurable as parameters to the top-level ccip_async_shim() module. The default buffer sizes maximize CCI-P throughput in typical AFU configurations.

The shim tracks outstanding requests in order to avoid oversubscribing the CCI-P response buffers. Buffer credits are enforced using standard CCI-P almost full flow control signals.

Instantiation

Connect platform (blue bitstream) to AFU (green bitstream) CCI-P structures with the top-level module, ccip_async_shim, defined in ccip_async_shim.sv:

module ccip_async_shim
  #(
    parameter DEBUG_ENABLE          = 0,
    parameter ENABLE_EXTRA_PIPELINE = 1,
    parameter C0TX_DEPTH_RADIX      = 8,
    parameter C1TX_DEPTH_RADIX      = 8,
    parameter C2TX_DEPTH_RADIX      = 8,
    parameter C0RX_DEPTH_RADIX      = 10,
    parameter C1RX_DEPTH_RADIX      = 10
    )
   (
    // ---------------------------------- //
    // Blue Bitstream Interface
    // ---------------------------------- //
    input logic        bb_softreset,
    input logic        bb_clk,
    output             t_if_ccip_Tx bb_tx,
    input              t_if_ccip_Rx bb_rx,
    // ---------------------------------- //
    // Green Bitstream interface
    // ---------------------------------- //
    output logic       afu_softreset,
    input logic        afu_clk,
    input              t_if_ccip_Tx afu_tx,
    output             t_if_ccip_Rx afu_rx,
    // ---------------------------------- //
    // Error vector
    // ---------------------------------- //
    output logic [4:0] async_shim_error
    );

The error vector, async_shim_error, contains one bit per channel. An error bit goes high in a cycle when data arrives but the corresponding channel buffer is full.

Importing sources for simulation or synthesis

For simulation, include BBB_ccip_async/hw/sim/ccip_async_sim_addenda.txt.

For synthesis, include BBB_ccip_async/hw/par/ccip_async_addenda.qsf. In addition to including the required source files, the QSF file imports BBB_ccip_async/hw/par/ccip_async.sdc -- a Tcl script that automatically discovers and assigns proper Quartus timing constraints to all instances of the clock-crossing shim.

Example

The sample CCI-P AFU platform interface, cci_afu_with_mpf.sv, instantiates a clock crossing shim. It picks an AFU clock given a desired target frequency. The example imports the clock crossing code into simulation in base_addenda.txt and into Quartus in cci_examples_base_PAR_files.qsf. Both import modules depend on the environment variable "FPGA_BBB_CCI_SRC", which must point to the root of the BBB source tree.