Getting open loop control and basic DMA path

[nwdepatie]

Changes

This commit is ginormous I am so sorry

1. Ported open loop control from dev kit to actual platform
2. Hooked up ADC interrupt to queue data to controller
3. Created PWM actor task that actually writes the PWM data
4. Initialized controller for both motors
5. Created and verified shared memory between the processors
6. Hooked up DMA stream to both pieces of shared memory
7. Created IPCC interface to abstract comms between cores
8. Hooked up hardware semaphores for alerting other core
9. Added in microsecond timer
10. Fixed FOC control pointer stuff

Notes

I am so sorry for the size of this commit I got carried away and just did stuff.

Note that IPCC comms are NOT fully verified yet. There are a lot of different ways of doing this and I want to really get a good idea of what responsibilities we should designate to each core. I think I am heavily leaning towards having the core be used solely for diagnostics and runtime behavior analysis. (i.e. CAN bus interface, serial interface, plotting task performance, monitoring temperatures, etc). That way we can kinda have them both running separate and not super dependent on eachother but still have them be extremely advantageous to use.

Test Cases

• Tested write and read to and from each piece of shared memory

To Do

Any remaining things that need to get done

• Hardware semaphore only triggers interrupt once
• DMA only triggers interrupt once
• Actually rounding out the internals of IPCC
• Tuning open loop control of motor
• Validating FOC control (might suck a lot)