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[Backport to 12] Support SPV_INTEL_maximum_registers extension (#2344) #2400

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merged 7 commits into from
Mar 19, 2024
Merged

[Backport to 12] Support SPV_INTEL_maximum_registers extension (#2344) #2400

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23658df
[Backport to 12] Support SPV_INTEL_maximum_registers extension (#2344)
vmaksimo Feb 26, 2024
6162183
Headers support
KorovinVlad Mar 4, 2024
40ce165
Headers support v2
KorovinVlad Mar 4, 2024
e0abd9e
Headers fixup
KorovinVlad Mar 4, 2024
3f908ce
Fix clang-tidy
KorovinVlad Mar 5, 2024
b9c9b67
Remove static_cast
KorovinVlad Mar 18, 2024
0d0e281
Revert "Remove static_cast"
KorovinVlad Mar 19, 2024
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5 changes: 2 additions & 3 deletions .clang-tidy
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
Checks: '-*,clang-diagnostic-*,llvm-*,misc-*,-misc-unused-parameters,readability-identifier-naming,-llvm-header-guard'
WarningsAsErrors: 'llvm-*,misc-*,-misc-unused-parameters,readability-identifier-naming,-llvm-header-guard'
Checks: '-*,clang-diagnostic-*,llvm-*,misc-*,-misc-no-recursion,-misc-unused-parameters,readability-identifier-naming,-llvm-header-guard'
WarningsAsErrors: 'llvm-*,misc-*,-misc-no-recursion,-misc-unused-parameters,readability-identifier-naming,-llvm-header-guard'
CheckOptions:
- key: readability-identifier-naming.ClassCase
value: CamelCase
Expand All @@ -17,4 +17,3 @@ CheckOptions:
value: CamelCase
- key: llvm-namespace-comment.ShortNamespaceLines
value: '25'

1 change: 1 addition & 0 deletions include/LLVMSPIRVExtensions.inc
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Expand Up @@ -47,3 +47,4 @@ EXT(SPV_INTEL_tensor_float32_conversion) // TODO: to remove old extension
EXT(SPV_INTEL_tensor_float32_rounding)
EXT(SPV_INTEL_hw_thread_queries)
EXT(SPV_EXT_relaxed_printf_string_address_space)
EXT(SPV_INTEL_maximum_registers)
42 changes: 42 additions & 0 deletions lib/SPIRV/SPIRVReader.cpp
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Expand Up @@ -3583,6 +3583,48 @@ bool SPIRVToLLVM::transMetadata() {
F->setMetadata(kSPIR2MD::FmaxMhz,
getMDNodeStringIntVec(Context, EM->getLiterals()));
}
if (auto *EM = BF->getExecutionMode(ExecutionModeMaximumRegistersINTEL)) {
NamedMDNode *ExecModeMD =
M->getOrInsertNamedMetadata(kSPIRVMD::ExecutionMode);

SmallVector<Metadata *, 4> ValueVec;
ValueVec.push_back(ConstantAsMetadata::get(F));
ValueVec.push_back(
ConstantAsMetadata::get(getUInt32(M, EM->getExecutionMode())));
ValueVec.push_back(
ConstantAsMetadata::get(getUInt32(M, EM->getLiterals()[0])));
ExecModeMD->addOperand(MDNode::get(*Context, ValueVec));
}
if (auto *EM = BF->getExecutionMode(ExecutionModeMaximumRegistersIdINTEL)) {
NamedMDNode *ExecModeMD =
M->getOrInsertNamedMetadata(kSPIRVMD::ExecutionMode);

SmallVector<Metadata *, 4> ValueVec;
ValueVec.push_back(ConstantAsMetadata::get(F));
ValueVec.push_back(
ConstantAsMetadata::get(getUInt32(M, EM->getExecutionMode())));

auto *ExecOp = BF->getModule()->getValue(EM->getLiterals()[0]);
ValueVec.push_back(
MDNode::get(*Context, ConstantAsMetadata::get(cast<ConstantInt>(
transValue(ExecOp, nullptr, nullptr)))));
ExecModeMD->addOperand(MDNode::get(*Context, ValueVec));
}
if (auto *EM =
BF->getExecutionMode(ExecutionModeNamedMaximumRegistersINTEL)) {
NamedMDNode *ExecModeMD =
M->getOrInsertNamedMetadata(kSPIRVMD::ExecutionMode);

SmallVector<Metadata *, 4> ValueVec;
ValueVec.push_back(ConstantAsMetadata::get(F));
ValueVec.push_back(
ConstantAsMetadata::get(getUInt32(M, EM->getExecutionMode())));

assert(EM->getLiterals()[0] == 0 &&
"Invalid named maximum number of registers");
ValueVec.push_back(MDString::get(*Context, "AutoINTEL"));
ExecModeMD->addOperand(MDNode::get(*Context, ValueVec));
}
}
NamedMDNode *MemoryModelMD =
M->getOrInsertNamedMetadata(kSPIRVMD::MemoryModel);
Expand Down
87 changes: 63 additions & 24 deletions lib/SPIRV/SPIRVWriter.cpp
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Expand Up @@ -671,6 +671,9 @@ SPIRVFunction *LLVMToSPIRV::transFunctionDecl(Function *F) {

transFPGAFunctionMetadata(BF, F);

if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_maximum_registers))
transFunctionMetadataAsExecutionMode(BF, F);

SPIRVDBG(dbgs() << "[transFunction] " << *F << " => ";
spvdbgs() << *BF << '\n';)
return BF;
Expand Down Expand Up @@ -769,6 +772,38 @@ void LLVMToSPIRV::transFPGAFunctionMetadata(SPIRVFunction *BF, Function *F) {
}
}

void LLVMToSPIRV::transFunctionMetadataAsExecutionMode(SPIRVFunction *BF,
Function *F) {
SmallVector<MDNode *, 1> RegisterAllocModeMDs;
F->getMetadata("RegisterAllocMode", RegisterAllocModeMDs);

for (unsigned I = 0; I < RegisterAllocModeMDs.size(); I++) {
auto *RegisterAllocMode = RegisterAllocModeMDs[I]->getOperand(0).get();
if (isa<MDString>(RegisterAllocMode)) {
const std::string Str = getMDOperandAsString(RegisterAllocModeMDs[I], 0);
const NamedMaximumNumberOfRegisters NamedValue =
SPIRVNamedMaximumNumberOfRegistersNameMap::rmap(Str);
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
OpExecutionMode, BF, ExecutionModeNamedMaximumRegistersINTEL,
NamedValue)));
} else if (isa<MDNode>(RegisterAllocMode)) {
auto *RegisterAllocNodeMDOp =
getMDOperandAsMDNode(RegisterAllocModeMDs[I], 0);
const int Num = getMDOperandAsInt(RegisterAllocNodeMDOp, 0);
auto *Const =
BM->addConstant(transType(Type::getInt32Ty(F->getContext())), Num);
BF->addExecutionMode(BM->add(new SPIRVExecutionModeId(
BF, ExecutionModeMaximumRegistersIdINTEL, Const->getId())));
} else {
const int64_t RegisterAllocVal =
mdconst::dyn_extract<ConstantInt>(RegisterAllocMode)->getZExtValue();
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
OpExecutionMode, BF, ExecutionModeMaximumRegistersINTEL,
RegisterAllocVal)));
}
}
}

SPIRVValue *LLVMToSPIRV::transConstant(Value *V) {
if (auto CPNull = dyn_cast<ConstantPointerNull>(V))
return BM->addNullConstant(
Expand Down Expand Up @@ -3669,14 +3704,14 @@ bool LLVMToSPIRV::transExecutionMode() {

switch (EMode) {
case spv::ExecutionModeContractionOff:
BF->addExecutionMode(BM->add(
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode))));
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode))));
break;
case spv::ExecutionModeInitializer:
case spv::ExecutionModeFinalizer:
if (BM->isAllowedToUseVersion(VersionNumber::SPIRV_1_1)) {
BF->addExecutionMode(BM->add(
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode))));
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode))));
} else {
getErrorLog().checkError(false, SPIRVEC_Requires1_1,
"Initializer/Finalizer Execution Mode");
Expand All @@ -3688,33 +3723,34 @@ bool LLVMToSPIRV::transExecutionMode() {
unsigned X, Y, Z;
N.get(X).get(Y).get(Z);
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
BF, static_cast<ExecutionMode>(EMode), X, Y, Z)));
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode), X, Y, Z)));
} break;
case spv::ExecutionModeMaxWorkgroupSizeINTEL: {
if (BM->isAllowedToUseExtension(
ExtensionID::SPV_INTEL_kernel_attributes)) {
unsigned X, Y, Z;
N.get(X).get(Y).get(Z);
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
BF, static_cast<ExecutionMode>(EMode), X, Y, Z)));
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode), X, Y,
Z)));
BM->addCapability(CapabilityKernelAttributesINTEL);
}
} break;
case spv::ExecutionModeNoGlobalOffsetINTEL: {
if (BM->isAllowedToUseExtension(
ExtensionID::SPV_INTEL_kernel_attributes)) {
BF->addExecutionMode(BM->add(
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode))));
BM->addCapability(CapabilityKernelAttributesINTEL);
}
if (!BM->isAllowedToUseExtension(
ExtensionID::SPV_INTEL_kernel_attributes))
break;
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode))));
BM->addCapability(CapabilityKernelAttributesINTEL);
} break;
case spv::ExecutionModeVecTypeHint:
case spv::ExecutionModeSubgroupSize:
case spv::ExecutionModeSubgroupsPerWorkgroup: {
unsigned X;
N.get(X);
BF->addExecutionMode(BM->add(
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode), X)));
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode), X)));
} break;
case spv::ExecutionModeNumSIMDWorkitemsINTEL:
case spv::ExecutionModeSchedulerTargetFmaxMhzINTEL:
Expand All @@ -3724,7 +3760,7 @@ bool LLVMToSPIRV::transExecutionMode() {
unsigned X;
N.get(X);
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
BF, static_cast<ExecutionMode>(EMode), X)));
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode), X)));
BM->addCapability(CapabilityFPGAKernelAttributesINTEL);
}
} break;
Expand All @@ -3734,15 +3770,16 @@ bool LLVMToSPIRV::transExecutionMode() {
unsigned SLMSize;
N.get(SLMSize);
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
BF, static_cast<ExecutionMode>(EMode), SLMSize)));
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode), SLMSize)));
} break;
case spv::ExecutionModeNamedBarrierCountINTEL: {
if (!BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_vector_compute))
break;
unsigned NBarrierCnt = 0;
N.get(NBarrierCnt);
BF->addExecutionMode(new SPIRVExecutionMode(
BF, static_cast<ExecutionMode>(EMode), NBarrierCnt));
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode),
NBarrierCnt)));
BM->addExtension(ExtensionID::SPV_INTEL_vector_compute);
BM->addCapability(CapabilityVectorComputeINTEL);
} break;
Expand All @@ -3757,7 +3794,8 @@ bool LLVMToSPIRV::transExecutionMode() {
unsigned TargetWidth;
N.get(TargetWidth);
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
BF, static_cast<ExecutionMode>(EMode), TargetWidth)));
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode),
TargetWidth)));
} break;
case spv::ExecutionModeRoundingModeRTPINTEL:
case spv::ExecutionModeRoundingModeRTNINTEL:
Expand All @@ -3769,12 +3807,13 @@ bool LLVMToSPIRV::transExecutionMode() {
unsigned TargetWidth;
N.get(TargetWidth);
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
BF, static_cast<ExecutionMode>(EMode), TargetWidth)));
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode),
TargetWidth)));
} break;
case spv::ExecutionModeFastCompositeKernelINTEL: {
if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_fast_composite))
BF->addExecutionMode(BM->add(
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode))));
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
OpExecutionMode, BF, static_cast<ExecutionMode>(EMode))));
} break;
default:
llvm_unreachable("invalid execution mode");
Expand Down Expand Up @@ -3819,8 +3858,8 @@ void LLVMToSPIRV::transFPContract() {
}

if (DisableContraction) {
BF->addExecutionMode(BF->getModule()->add(
new SPIRVExecutionMode(BF, spv::ExecutionModeContractionOff)));
BF->addExecutionMode(BF->getModule()->add(new SPIRVExecutionMode(
OpExecutionMode, BF, spv::ExecutionModeContractionOff)));
}
}
}
Expand Down
1 change: 1 addition & 0 deletions lib/SPIRV/SPIRVWriter.h
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Expand Up @@ -118,6 +118,7 @@ class LLVMToSPIRV : public ModulePass {
SPIRVFunction *transFunctionDecl(Function *F);
void transVectorComputeMetadata(Function *F);
void transFPGAFunctionMetadata(SPIRVFunction *BF, Function *F);
void transFunctionMetadataAsExecutionMode(SPIRVFunction *BF, Function *F);
bool transGlobalVariables();

Op transBoolOpCode(SPIRVValue *Opn, Op OC);
Expand Down
10 changes: 7 additions & 3 deletions lib/SPIRV/libSPIRV/SPIRVEntry.cpp
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Expand Up @@ -532,7 +532,7 @@ SPIRVEntryPoint::SPIRVEntryPoint(SPIRVModule *TheModule,
SPIRVExecutionModelKind TheExecModel,
SPIRVId TheId, const std::string &TheName,
std::vector<SPIRVId> Variables)
: SPIRVAnnotation(TheModule->get<SPIRVFunction>(TheId),
: SPIRVAnnotation(OpEntryPoint, TheModule->get<SPIRVFunction>(TheId),
getSizeInWords(TheName) + Variables.size() + 3),
ExecModel(TheExecModel), Name(TheName), Variables(Variables) {}

Expand All @@ -552,7 +552,7 @@ void SPIRVExecutionMode::encode(spv_ostream &O) const {

void SPIRVExecutionMode::decode(std::istream &I) {
getDecoder(I) >> Target >> ExecMode;
switch (ExecMode) {
switch (static_cast<uint32_t>(ExecMode)) {
case ExecutionModeLocalSize:
case ExecutionModeLocalSizeHint:
case ExecutionModeMaxWorkgroupSizeINTEL:
Expand All @@ -576,6 +576,9 @@ void SPIRVExecutionMode::decode(std::istream &I) {
case ExecutionModeMaxWorkDimINTEL:
case ExecutionModeNumSIMDWorkitemsINTEL:
case ExecutionModeSchedulerTargetFmaxMhzINTEL:
case ExecutionModeMaximumRegistersINTEL:
case ExecutionModeMaximumRegistersIdINTEL:
case ExecutionModeNamedMaximumRegistersINTEL:
WordLiterals.resize(1);
break;
default:
Expand All @@ -597,7 +600,8 @@ SPIRVForward *SPIRVAnnotationGeneric::getOrCreateTarget() const {
}

SPIRVName::SPIRVName(const SPIRVEntry *TheTarget, const std::string &TheStr)
: SPIRVAnnotation(TheTarget, getSizeInWords(TheStr) + 2), Str(TheStr) {}
: SPIRVAnnotation(OpName, TheTarget, getSizeInWords(TheStr) + 2),
Str(TheStr) {}

void SPIRVName::encode(spv_ostream &O) const { getEncoder(O) << Target << Str; }

Expand Down
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