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Pull requests: FPGA-Research/FABulous

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Pull requests list

Fix config bit after #242
#314 opened Feb 4, 2025 by KelvinChung2000 Loading…
3
Fix VHDL simulation, cleanup VHDL project template, add VHDL action
#312 opened Feb 3, 2025 by EverythingElseWasAlreadyTaken Loading…
5
Include first/last row in bitstream generation and ConfigFSM
#311 opened Feb 3, 2025 by mole99 Loading…
Add generative IOs
#253 opened Nov 21, 2024 by EverythingElseWasAlreadyTaken • Draft
6
Vhdl simulation
#214 opened Jul 29, 2024 by Biswajitks1 • Draft
23
Fix FrameData wiring for NULL tiles at the border
#161 opened Feb 22, 2024 by mole99 Loading…
2
Ngi0 reuse
#105 opened Jul 28, 2023 by Jit-p Loading…
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