Add generative IOs #253
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Adds a GEN_IO primitive to generate IOs in the top level design and route them trough to the defined tile, where they are connected to the switchmatrix. GEN_IOs can be used as following in the fabric.csv: GEN_IO,Number of Pins,Direction,Prefix ``` fabric.csv:: GEN_IO,2,OUTPUT,A_O,,,,,,,,,,,,,, GEN_IO,2,INPUT,A_I,,,,,,,,,,,,,, ``` This will generate four IOs, two INPUT (A_I0, A_I1) and two OUTPUT(A_O0 and A_O1), which can be a accessed in the tile through the switchmatrix. This will also generate four external ports, (A_I0_top, A_I1_top, A_O0_top, A_O1_top) which are routed to the top level and are connected to the equivalent tile ports. Signed-off-by: Jonas K. <[email protected]>
Adds the CONFIGACCESS flag to GEN_IO which allows us to generate config access bits directly for a tile. ``` fabric.csv:: GEN_IO,2,OUTPUT,C_,CONFIGACCESS,,,,,,,,,,,,, ``` Will generate 2 config access bits for this tile, that will be routed to Top. Signed-off-by: Jonas K. <[email protected]>
Add inverted feature, to invert a GEN_IO. ``` fabric.csv:: GEN_IO,2,OUTPUT,A_O_,INVERTED,,,,,,,,,,,,, ``` Will generate 2 Output ports for the fabric, that are inverted. Can be also used with config access: ``` fabric.csv:: GEN_IO,2,OUTPUT,C_,CONFIGACCESS,INVERTED,,,,,,,,,,,, ``` Signed-off-by: Jonas K. <[email protected]>
Add AddRegister command to VHDL and Verilog writer, which adds a Register. Add clocked feature to GEN_IO, which adds a register to GEN_IO. ``` fabric.csv: GEN_IO,2,OUTPUT,A_C_,CLOCKED,,,,,,,,,,,,, ``` Adds two clocked output GEN_IOs to a tile. Convert GEN_IO docsting to new format. Signed-off-by: Jonas K. <[email protected]>
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@KelvinChung2000 Please no squash merge on this, since there are a lot of change, so it would be good to keep the commits separated, for a better traceability and to keep the commit messages. |
Add documentation for generative IOs Signed-off-by: Jonas K. <[email protected]>
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| @@ -21,6 +22,8 @@ class Tile: | |||
| The list of ports of the tile | |||
| matrixDir : str | |||
| The directory of the tile matrix | |||
| gen_ios : (List[Gen_IO]) | |||
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should not need bracket
| @@ -35,6 +38,7 @@ class Tile: | |||
| portsInfo: list[Port] | |||
| bels: list[Bel] | |||
| matrixDir: pathlib.Path | |||
| gen_ios = list[Gen_IO] | |||
| @@ -108,20 +108,38 @@ def addLogicStart(self, indentLevel=0): | |||
| def addLogicEnd(self, indentLevel=0): | |||
| self._add("\n" f"end" "\n", indentLevel) | |||
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| def addAssignScalar(self, left, right, delay=0, indentLevel=0): | |||
| def addRegister(self, reg, regIn, clk="CLK", inverted=False, indentLevel=0): | |||
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For large text templates, I think putting the text at the top and then using .format should make things look cleaner. We can do this sort of "cosmetic" update later
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Adding information about the created port still needs information would be useful.
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Adds a GEN_IO primitive to generate IOs in the top level design and
route them trough to the defined tile, where they are connected to
the switchmatrix.
GEN_IOs can be used as following in the fabric.csv:
GEN_IO,Number of Pins,Direction,Prefix
This will generate four IOs, two INPUT (A_I0, A_I1) and two OUTPUT(A_O0
and A_O1), which can be a accessed in the tile through the switchmatrix.
This will also generate four external ports, (A_I0_top, A_I1_top,
A_O0_top, A_O1_top) which are routed to the top level and are connected
to the equivalent tile ports.