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i#5725: Set consistent x86 vendor decoding default #6438

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merged 3 commits into from
Nov 10, 2023
Merged

i#5725: Set consistent x86 vendor decoding default #6438

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c3f4870
i#5725: Set consistent x86 vendor decoding default
derekbruening Nov 9, 2023
cd0cc6f
For standalone_library, set vendor to VENDOR_INTEL in proc_init
derekbruening Nov 9, 2023
9a5ddc6
Move intel override to after cpuid queries
derekbruening Nov 9, 2023
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41 changes: 26 additions & 15 deletions core/arch/proc_shared.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/* **********************************************************
* Copyright (c) 2013-2022 Google, Inc. All rights reserved.
* Copyright (c) 2013-2023 Google, Inc. All rights reserved.
* Copyright (c) 2000-2008 VMware, Inc. All rights reserved.
* **********************************************************/

Expand Down Expand Up @@ -63,25 +63,36 @@
*/
size_t cache_line_size = 32;
static ptr_uint_t mask; /* bits that should be 0 to be cache-line-aligned */
cpu_info_t cpu_info = { VENDOR_UNKNOWN,
cpu_info_t cpu_info = {
#ifdef X86
/* If we initialize to VENDOR_UNKNOWN we get contradictory decoding results
* for opcodes that vary between VENDOR_AMD and VENDOR_INTEL (because some
* of our decoding code checks one and some checks the other) so we pick one
* for a stable self-consistent default.
*/
VENDOR_INTEL,
#else
VENDOR_UNKNOWN,
#endif
#ifdef AARCHXX
0,
0,
0,
0,
#endif
0,
0,
0,
0,
CACHE_SIZE_UNKNOWN,
CACHE_SIZE_UNKNOWN,
CACHE_SIZE_UNKNOWN,
0,
0,
0,
0,
CACHE_SIZE_UNKNOWN,
CACHE_SIZE_UNKNOWN,
CACHE_SIZE_UNKNOWN,
#if defined(RISCV64)
/* FIXME i#3544: Not implemented */
{ 0 },
/* FIXME i#3544: Not implemented */
{ 0 },
#else
{ 0, 0, 0, 0 },
{ 0, 0, 0, 0 },
#endif
{ 0x6e6b6e75, 0x006e776f } };
{ 0x6e6b6e75, 0x006e776f }
};

void
proc_set_cache_size(uint val, uint *dst)
Expand Down
17 changes: 16 additions & 1 deletion core/arch/x86/proc.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/* **********************************************************
* Copyright (c) 2013-2022 Google, Inc. All rights reserved.
* Copyright (c) 2013-2023 Google, Inc. All rights reserved.
* Copyright (c) 2000-2008 VMware, Inc. All rights reserved.
* **********************************************************/

Expand Down Expand Up @@ -333,6 +333,21 @@ get_processor_specific_info(void)
our_cpuid((int *)&cpu_info.brand_string[4], 0x80000003, 0);
our_cpuid((int *)&cpu_info.brand_string[8], 0x80000004, 0);
}

if (standalone_library) {
/* For separate decoding, keep a base default and do not target the
* underlying processor (xref i#431, i#6420, i#5725).
* The user can use proc_set_vendor() to override.
* This affects various decoding corner cases and is important to set.
* We leave all the other cache info, etc. pointing to the current hardware.
* We set this at the end here to avoid errors in getting other
* cpuid values with the wrong magic parameters.
* XXX: This is still potentially fragile; should the decoder have
* a separate vendor value?
*/
LOG(GLOBAL, LOG_TOP, 1, "For standalone decoding, assuming Intel target.\n");
cpu_info.vendor = VENDOR_INTEL;
}
}

/* arch specific proc info */
Expand Down
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