i#2626: AArch64 v8.0 decode: Add SQSHL, SHL and SLI

core/ir/aarch64/codec.c

@@ -2733,6 +2733,58 @@ encode_opnd_immhb_shf(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc
     return true;
 }
 
+/* immhb_shf2: The vector encoding of #shift operand.
+ */
+static inline bool
+decode_opnd_immhb_0shf(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
+{
+    int highest_bit;
+    if (!highest_bit_set(enc, 19, 4, &highest_bit))
+        return false;
+
+    uint esize = 8 << highest_bit;
+    uint immhb_shf = extract_uint(enc, 16, 4 + highest_bit);
+    opnd_size_t shift_size;
+    switch (highest_bit) {
+    case 0: shift_size = OPSZ_3b; break;
+    case 1: shift_size = OPSZ_4b; break;
+    case 2: shift_size = OPSZ_5b; break;
+    case 3: shift_size = OPSZ_6b; break;
+    default: return false;
+    }
+
+    *opnd = opnd_create_immed_int(immhb_shf - esize, shift_size);
+    opnd_add_flags(*opnd, DR_OPND_IS_SHIFT);
+    return true;
+}
+
+static inline bool
+encode_opnd_immhb_0shf(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
+{
+    opnd_size_t shift_size = opnd_get_size(opnd);
+    uint highest_bit;
+    switch (shift_size) {
+    case OPSZ_3b: highest_bit = 0; break;
+    case OPSZ_4b: highest_bit = 1; break;
+    case OPSZ_5b: highest_bit = 2; break;
+    case OPSZ_6b: highest_bit = 3; break;
+    default: return false;
+    }
+    ptr_int_t shift_amount;
+    uint esize = 8 << highest_bit;
+
+    if (!opnd_is_immed_int(opnd))
+        return false;
+
+    shift_amount = opnd_get_immed_int(opnd);
+    if (shift_amount < 0 || shift_amount > (esize - 1))
+        return false;
+
+    *enc_out = ((shift_amount + esize) << 16);
+
+    return true;
+}
+
 /* fpimm13: floating-point immediate for scalar fmov */
 
 static inline bool

core/ir/aarch64/codec.txt

@@ -147,6 +147,7 @@
                                              # elements, depending on bit 22 (sz)
 ---------x----------------------  sd_sz      # element width of FP vector reg for single
 ---------xxxxxxx----------------  immhb_shf  # encoding of #shift value in immh:immb fields
+---------xxxxxxx----------------  immhb_0shf # encoding of #shift value in zero-indexed immh:immb fields
 --------??-xxxxxxxx-------------  fpimm13    # floating-point immediate for scalar fmov
 --------xx----------------------  b_sz       # element width of a vector (8<<b_sz)
 --------xx----------------------  hs_sz      # element width of a vector (8<<hs_sz)
@@ -1108,8 +1109,11 @@ x101101011000000000101xxxxxxxxxx  n  cls     wx0 : wx5
 01011110011xxxxx010011xxxxxxxxxx  n     sqshl      h0 : h5 h16
 01011110101xxxxx010011xxxxxxxxxx  n     sqshl      s0 : s5 s16
 01011110111xxxxx010011xxxxxxxxxx  n     sqshl      d0 : d5 d16
-0101111100xxxxxx011101xxxxxxxxxx  n     sqshl      s0 : s5 immhb_fxp
-0101111101xxxxxx011101xxxxxxxxxx  n     sqshl      d0 : d5 immhb_fxp
+0101111100001xxx011101xxxxxxxxxx  n     sqshl      b0 : b5 immhb_0shf
+010111110001xxxx011101xxxxxxxxxx  n     sqshl      h0 : h5 immhb_0shf
+01011111001xxxxx011101xxxxxxxxxx  n     sqshl      s0 : s5 immhb_0shf
+0101111101xxxxxx011101xxxxxxxxxx  n     sqshl      d0 : d5 immhb_0shf
+0x0011110xxxxxxx011101xxxxxxxxxx  n     sqshl     dq0 : dq5 bhsd_immh_sz immhb_0shf
 0x001110xx1xxxxx010101xxxxxxxxxx  n     srshl     dq0 : dq5 dq16 bhsd_sz
 0x001110xx1xxxxx010111xxxxxxxxxx  n     sqrshl    dq0 : dq5 dq16 bhsd_sz
 0x001110xx1xxxxx011001xxxxxxxxxx  n     smax      dq0 : dq5 dq16 bhs_sz
@@ -1569,8 +1573,10 @@ x001111001000010xxxxxxxxxxxxxxxx  n     scvtf     d0 : wx5 scale
 0101111101xxxxxx000001xxxxxxxxxx  n     sshr       d0 : d5 immhb_fxp
 0x0011110xxxxxxx000001xxxxxxxxxx  n     sshr      dq0 : dq5 sd_sz immhb_fxp
 0101111101xxxxxx000101xxxxxxxxxx  n     ssra       d0 : d5 immhb_fxp
-0101111101xxxxxx010101xxxxxxxxxx  n     shl        d0 : d5 immhb_fxp
-0111111101xxxxxx010101xxxxxxxxxx  n     sli        d0 : d5 immhb_fxp
+0101111101xxxxxx010101xxxxxxxxxx  n     shl        d0 : d5 immhb_0shf
+0x0011110xxxxxxx010101xxxxxxxxxx  n     shl       dq0 : dq5 bhsd_immh_sz immhb_0shf
+0111111101xxxxxx010101xxxxxxxxxx  n     sli        d0 : d5 immhb_0shf
+0x1011110xxxxxxx010101xxxxxxxxxx  n     sli       dq0 : dq5 bhsd_immh_sz immhb_0shf
 0111111101xxxxxx000001xxxxxxxxxx  n     ushr       d0 : d5 immhb_shf
 0x1011110xxxxxxx000001xxxxxxxxxx  n     ushr      dq0 : dq5 bhsd_immh_sz immhb_shf
 0111111101xxxxxx000101xxxxxxxxxx  n     usra       d0 : d5 immhb_fxp

core/ir/aarch64/instr_create_api.h

@@ -1784,6 +1784,18 @@ enum {
 #define INSTR_CREATE_fcvtzu_vector_fixed(dc, Rd, Rm, width, fbits) \
     instr_create_1dst_3src(dc, OP_fcvtzu, Rd, Rm, width, fbits)
 
+/**
+ * Creates an SLI shift left and insert instruction.
+ * \param dc      The void * dcontext used to allocate memory for the #instr_t.
+ * \param Rd      The output register.
+ * \param Rn      The input register.
+ * \param width   The output vector element width. Use OPND_CREATE_BYTE(),
+ *                OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
+ * \param shift   The number of bits to shift the result by.
+ */
+#define INSTR_CREATE_sli_vector(dc, Rd, Rn, width, shift) \
+    instr_create_1dst_3src(dc, OP_sli, Rd, Rn, width, shift)
+
 /**
  * Creates an UQSHRN vector unsigned saturating shift right narrow (immediate)
  * instruction.