DynamoRIO · abhinav92003 · Jul 20, 2020 · Jun 29, 2020 · Jun 29, 2020 · Jun 29, 2020
diff --git a/clients/drcachesim/common/trace_entry.cpp b/clients/drcachesim/common/trace_entry.cpp
@@ -65,4 +65,22 @@ const char *const trace_type_names[] = {
     "non-fetched instr",
     "maybe-fetched instr",
     "sysenter",
+    "prefetch_pldl1keep",
+    "prefetch_pldl1strm",
+    "prefetch_pldl2keep",
+    "prefetch_pldl2strm",
+    "prefetch_pldl3keep",
+    "prefetch_pldl3strm",
+    "prefetch_plil1keep",
+    "prefetch_plil1strm",
+    "prefetch_plil2keep",
+    "prefetch_plil2strm",
+    "prefetch_plil3keep",
+    "prefetch_plil3strm",
+    "prefetch_pstl1keep",
+    "prefetch_pstl1strm",
+    "prefetch_pstl2keep",
+    "prefetch_pstl2strm",
+    "prefetch_pstl3keep",
+    "prefetch_pstl3strm",
 };
diff --git a/clients/drcachesim/common/trace_entry.h b/clients/drcachesim/common/trace_entry.h
@@ -163,6 +163,49 @@ typedef enum {
      */
     TRACE_TYPE_INSTR_SYSENTER,
 
+    /** AArch64 specific prefetch trace entries.
+     *  Relative order of these enum values is relevant to the handling of AArch64
+     * prefetch instructions.
+     */
+    TRACE_TYPE_PREFETCH_PLDL1KEEP, /**< An AArch64 load prefetch to level 1 of the cache.
+                                    */
+    TRACE_TYPE_PREFETCH_PLDL1STRM, /**< An AArch64 streaming load prefetch to level 1 of
+                                      the cache. */
+    TRACE_TYPE_PREFETCH_PLDL2KEEP, /**< An AArch64 load prefetch to level 2 of the cache.
+                                    */
+    TRACE_TYPE_PREFETCH_PLDL2STRM, /**< An AArch64 streaming load prefetch to level 2 of
+                                      the cache. */
+    TRACE_TYPE_PREFETCH_PLDL3KEEP, /**< An AArch64 load prefetch to level 3 of the cache.
+                                    */
+    TRACE_TYPE_PREFETCH_PLDL3STRM, /**< An AArch64 streaming load prefetch to level 3 of
+                                      the cache. */
+
+    TRACE_TYPE_PREFETCH_PLIL1KEEP, /**< An AArch64 instruction prefetch to level 1 of the
+                                      cache. */
+    TRACE_TYPE_PREFETCH_PLIL1STRM, /**< An AArch64 streaming instruction prefetch to level
+                                      1 of the cache. */
+    TRACE_TYPE_PREFETCH_PLIL2KEEP, /**< An AArch64 instruction prefetch to level 2 of the
+                                      cache. */
+    TRACE_TYPE_PREFETCH_PLIL2STRM, /**< An AArch64 streaming instruction prefetch to level
+                                      2 of the cache. */
+    TRACE_TYPE_PREFETCH_PLIL3KEEP, /**< An AArch64 instruction prefetch to level 3 of the
+                                      cache. */
+    TRACE_TYPE_PREFETCH_PLIL3STRM, /**< An AArch64 streaming instruction prefetch to level
+                                      3 of the cache. */
+
+    TRACE_TYPE_PREFETCH_PSTL1KEEP, /**< An AArch64 store prefetch to level 1 of the cache.
+                                    */
+    TRACE_TYPE_PREFETCH_PSTL1STRM, /**< An AArch64 streaming store prefetch to level 1 of
+                                      the cache. */
+    TRACE_TYPE_PREFETCH_PSTL2KEEP, /**< An AArch64 store prefetch to level 2 of the cache.
+                                    */
+    TRACE_TYPE_PREFETCH_PSTL2STRM, /**< An AArch64 streaming store prefetch to level 2 of
+                                      the cache. */
+    TRACE_TYPE_PREFETCH_PSTL3KEEP, /**< An AArch64 store prefetch to level 3 of the cache.
+                                    */
+    TRACE_TYPE_PREFETCH_PSTL3STRM, /**< An AArch64 streaming store prefetch to level 3 of
+                                      the cache. */
+
     // Update trace_type_names[] when adding here.
 } trace_type_t;
 
@@ -277,6 +320,8 @@ static inline bool
 type_is_prefetch(const trace_type_t type)
 {
     return (type >= TRACE_TYPE_PREFETCH && type <= TRACE_TYPE_PREFETCH_INSTR) ||
+        (type >= TRACE_TYPE_PREFETCH_PLDL1KEEP &&
+         type <= TRACE_TYPE_PREFETCH_PSTL3STRM) ||
         type == TRACE_TYPE_HARDWARE_PREFETCH;
 }
 

diff --git a/clients/drcachesim/reader/reader.cpp b/clients/drcachesim/reader/reader.cpp
@@ -78,6 +78,24 @@ reader_t::operator++()
         case TRACE_TYPE_PREFETCH_READ:
         case TRACE_TYPE_PREFETCH_WRITE:
         case TRACE_TYPE_PREFETCH_INSTR:
+        case TRACE_TYPE_PREFETCH_PLDL1KEEP:
+        case TRACE_TYPE_PREFETCH_PLDL1STRM:
+        case TRACE_TYPE_PREFETCH_PLDL2KEEP:
+        case TRACE_TYPE_PREFETCH_PLDL2STRM:
+        case TRACE_TYPE_PREFETCH_PLDL3KEEP:
+        case TRACE_TYPE_PREFETCH_PLDL3STRM:
+        case TRACE_TYPE_PREFETCH_PLIL1KEEP:
+        case TRACE_TYPE_PREFETCH_PLIL1STRM:
+        case TRACE_TYPE_PREFETCH_PLIL2KEEP:
+        case TRACE_TYPE_PREFETCH_PLIL2STRM:
+        case TRACE_TYPE_PREFETCH_PLIL3KEEP:
+        case TRACE_TYPE_PREFETCH_PLIL3STRM:
+        case TRACE_TYPE_PREFETCH_PSTL1KEEP:
+        case TRACE_TYPE_PREFETCH_PSTL1STRM:
+        case TRACE_TYPE_PREFETCH_PSTL2KEEP:
+        case TRACE_TYPE_PREFETCH_PSTL2STRM:
+        case TRACE_TYPE_PREFETCH_PSTL3KEEP:
+        case TRACE_TYPE_PREFETCH_PSTL3STRM:
             have_memref = true;
             assert(cur_tid_ != 0 && cur_pid_ != 0);
             cur_ref_.data.pid = cur_pid_;

diff --git a/clients/drcachesim/tests/offline-prefetch-aarch64-basic-counts.templatex b/clients/drcachesim/tests/offline-prefetch-aarch64-basic-counts.templatex
@@ -0,0 +1,31 @@
+Hello, world!
+Basic counts tool results:
+Total counts:
+     .* total \(fetched\) instructions
+     .* total unique \(fetched\) instructions
+     .* total non-fetched instructions
+          62 total prefetches
+     .* total data loads
+     .* total data stores
+           1 total threads
+     .* total scheduling markers
+     .* total transfer markers
+     .* total function id markers
+     .* total function return address markers
+     .* total function argument markers
+     .* total function return value markers
+     .* total other markers
+Thread .* counts:
+     .* \(fetched\) instructions
+     .* unique \(fetched\) instructions
+     .* non-fetched instructions
+          62 prefetches
+     .* data loads
+     .* data stores
+     .* scheduling markers
+     .* transfer markers
+     .* function id markers
+     .* function return address markers
+     .* function argument markers
+     .* function return value markers
+     .* other markers
diff --git a/clients/drcachesim/tests/offline-prefetch-basic-counts.templatex b/clients/drcachesim/tests/offline-prefetch-basic-counts.templatex
@@ -0,0 +1,43 @@
+Hello, world!
+Basic counts tool results:
+Total counts:
+     .* total \(fetched\) instructions
+     .* total unique \(fetched\) instructions
+     .* total non-fetched instructions
+#if defined(AARCH64)
+          34 total prefetches
+#elif defined(X86) && !defined(X64)
+           0 total prefetches
+#else
+           8 total prefetches
+#endif
+     .* total data loads
+     .* total data stores
+           1 total threads
+     .* total scheduling markers
+     .* total transfer markers
+     .* total function id markers
+     .* total function return address markers
+     .* total function argument markers
+     .* total function return value markers
+     .* total other markers
+Thread .* counts:
+     .* \(fetched\) instructions
+     .* unique \(fetched\) instructions
+     .* non-fetched instructions
+#if defined(AARCH64)
+          34 prefetches
+#elif defined(X86) && !defined(X64)
+           0 prefetches
+#else
+           8 prefetches
+#endif
+     .* data loads
+     .* data stores
+     .* scheduling markers
+     .* transfer markers
+     .* function id markers
+     .* function return address markers
+     .* function argument markers
+     .* function return value markers
+     .* other markers
diff --git a/clients/drcachesim/tests/prefetch-aarch64-basic-counts.templatex b/clients/drcachesim/tests/prefetch-aarch64-basic-counts.templatex
@@ -0,0 +1,32 @@
+Hello, world!
+---- <application exited with code 0> ----
+Basic counts tool results:
+Total counts:
+     .* total \(fetched\) instructions
+     .* total unique \(fetched\) instructions
+     .* total non-fetched instructions
+          62 total prefetches
+     .* total data loads
+     .* total data stores
+           1 total threads
+     .* total scheduling markers
+     .* total transfer markers
+     .* total function id markers
+     .* total function return address markers
+     .* total function argument markers
+     .* total function return value markers
+     .* total other markers
+Thread .* counts:
+     .* \(fetched\) instructions
+     .* unique \(fetched\) instructions
+     .* non-fetched instructions
+          62 prefetches
+     .* data loads
+     .* data stores
+     .* scheduling markers
+     .* transfer markers
+     .* function id markers
+     .* function return address markers
+     .* function argument markers
+     .* function return value markers
+     .* other markers
diff --git a/clients/drcachesim/tests/prefetch-basic-counts.templatex b/clients/drcachesim/tests/prefetch-basic-counts.templatex
@@ -0,0 +1,44 @@
+Hello, world!
+---- <application exited with code 0> ----
+Basic counts tool results:
+Total counts:
+     .* total \(fetched\) instructions
+     .* total unique \(fetched\) instructions
+     .* total non-fetched instructions
+#if defined(AARCH64)
+          34 total prefetches
+#elif defined(X86) && !defined(X64)
+           0 total prefetches
+#else
+           8 total prefetches
+#endif
+     .* total data loads
+     .* total data stores
+           1 total threads
+     .* total scheduling markers
+     .* total transfer markers
+     .* total function id markers
+     .* total function return address markers
+     .* total function argument markers
+     .* total function return value markers
+     .* total other markers
+Thread .* counts:
+     .* \(fetched\) instructions
+     .* unique \(fetched\) instructions
+     .* non-fetched instructions
+#if defined(AARCH64)
+          34 prefetches
+#elif defined(X86) && !defined(X64)
+           0 prefetches
+#else
+           8 prefetches
+#endif
+     .* data loads
+     .* data stores
+     .* scheduling markers
+     .* transfer markers
+     .* function id markers
+     .* function return address markers
+     .* function argument markers
+     .* function return value markers
+     .* other markers
diff --git a/clients/drcachesim/tracer/instru.cpp b/clients/drcachesim/tracer/instru.cpp
@@ -78,6 +78,51 @@ instru_t::instr_to_instr_type(instr_t *instr, bool repstr_expanded)
     return TRACE_TYPE_INSTR;
 }
 
+#ifdef AARCH64
+unsigned short
+get_aarch64_prefetch_target_policy(ptr_int_t prfop)
+{
+    // Least significant three bits of prfop represent prefetch target and
+    // policy [... b2 b1 b0]
+    //
+    // b2 b1 : prefetch target
+    // 0b00 - L1 cache, 0b01 - L2 cache, 0b10 - L3 cache
+    //
+    // b0 : prefetch policy
+    // 0b0 - temporal prefetch, 0b1 - streaming (non-temporal) prefetch
+    return prfop & 0b111;
+}
+
+unsigned short
+get_aarch64_prefetch_op_type(ptr_int_t prfop)
+{
+    // Bits at position 3 and 4 in prfop represent prefetch operation type
+    // [... b4 b3 ...]
+    // 0b00 - prefetch for load
+    // 0b01 - prefetch for instruction
+    // 0b10 - prefetch for store
+    return (prfop >> 3) & 0b11;
+}
+
+unsigned short
+get_aarch64_prefetch_type(ptr_int_t prfop)
+{
+    unsigned short target_policy = get_aarch64_prefetch_target_policy(prfop);
+    unsigned short op_type = get_aarch64_prefetch_op_type(prfop);
+    DR_ASSERT_MSG(target_policy < 6 && op_type < 3,
+                  "Unsupported AArch64 prefetch operation.");
+    switch (op_type) {
+    case 0: // prefetch for load
+        return TRACE_TYPE_PREFETCH_PLDL1KEEP + target_policy;
+    case 1: // prefetch for instruction
+        return TRACE_TYPE_PREFETCH_PLIL1KEEP + target_policy;
+    case 2: // prefetch for store
+        return TRACE_TYPE_PREFETCH_PSTL1KEEP + target_policy;
+    }
+    return TRACE_TYPE_PREFETCH; // unreachable.
+}
+#endif
+
 unsigned short
 instru_t::instr_to_prefetch_type(instr_t *instr)
 {
@@ -94,6 +139,12 @@ instru_t::instr_to_prefetch_type(instr_t *instr)
     case OP_pld: return TRACE_TYPE_PREFETCH_READ;
     case OP_pldw: return TRACE_TYPE_PREFETCH_WRITE;
     case OP_pli: return TRACE_TYPE_PREFETCH_INSTR;
+#endif
+#ifdef AARCH64
+    case OP_prfm:
+        return get_aarch64_prefetch_type(opnd_get_immed_int(instr_get_src(instr, 0)));
+    case OP_prfum:
+        return get_aarch64_prefetch_type(opnd_get_immed_int(instr_get_src(instr, 0)));
 #endif
     default: return TRACE_TYPE_PREFETCH;
     }

diff --git a/core/ir/aarch64/instr.c b/core/ir/aarch64/instr.c
@@ -246,8 +246,8 @@ instr_is_mov_constant(instr_t *instr, ptr_int_t *value)
 bool
 instr_is_prefetch(instr_t *instr)
 {
-    /* FIXME i#1569: NYI */
-    return false;
+    int opcode = instr_get_opcode(instr);
+    return opcode == OP_prfm || opcode == OP_prfum;
 }
 
 bool

diff --git a/suite/tests/CMakeLists.txt b/suite/tests/CMakeLists.txt
@@ -652,6 +652,20 @@ set(ci_shared_app simple_app)
 set(ci_shared_app_src client-interface/${ci_shared_app}.c)
 add_exe(${ci_shared_app} ${ci_shared_app_src})
 
+if (CMAKE_COMPILER_IS_GNUCC)
+  # An app with prefetch instructions.
+  set(ci_prefetch_app prefetch_app)
+  set(ci_prefetch_app_src client-interface/${ci_prefetch_app}.c)
+  add_exe(${ci_prefetch_app} ${ci_prefetch_app_src})
+endif ()
+
+if (AARCH64)
+  # An AArch64 app with prefetch instructions.
+  set(ci_prefetch_aarch64_app prefetch_aarch64_app)
+  set(ci_prefetch_aarch64_app_src client-interface/${ci_prefetch_aarch64_app}.c)
+  add_exe(${ci_prefetch_aarch64_app} ${ci_prefetch_aarch64_app_src})
+endif ()
+
 function(setup_test_client_dll_basics test)
   configure_DynamoRIO_client(${test})
   append_property_string(TARGET ${test} LINK_FLAGS "${ARCH_DEBUG}")
@@ -3108,6 +3122,15 @@ if (CLIENT_INTERFACE)
 
       torunonly_drcachesim(instr-only-trace ${ci_shared_app} "-instr_only_trace" "")
 
+      if (CMAKE_COMPILER_IS_GNUCC)
+        torunonly_drcachesim(prefetch-basic-counts ${ci_prefetch_app} "-simulator_type basic_counts" "")
+        unset(tool.drcachesim.prefetch-basic-counts_rawtemp) # use preprocessor
+      endif ()
+
+      if (AARCH64)
+        torunonly_drcachesim(prefetch-aarch64-basic-counts ${ci_prefetch_aarch64_app} "-simulator_type basic_counts" "")
+      endif ()
+
       torunonly_drcachesim(delay-simple ${ci_shared_app}
         "-trace_after_instrs 20000 -exit_after_tracing 10000" "")
 
@@ -3331,6 +3354,15 @@ if (CLIENT_INTERFACE)
       torunonly_drcacheoff(instr-only-trace ${ci_shared_app} "-instr_only_trace" "" "")
       torunonly_drcacheoff(filter-and-instr-only-trace ${ci_shared_app} "-instr_only_trace -L0_filter" "" "")
 
+      if (CMAKE_COMPILER_IS_GNUCC)
+        torunonly_drcacheoff(prefetch-basic-counts ${ci_prefetch_app} "" "@-simulator_type@basic_counts" "")
+        unset(tool.drcacheoff.prefetch-basic-counts_rawtemp) # use preprocessor
+      endif ()
+
+      if (AARCH64)
+        torunonly_drcacheoff(prefetch-aarch64-basic-counts ${ci_prefetch_aarch64_app} "" "@-simulator_type@basic_counts" "")
+      endif ()
+
       # We run common.decode-bad to test markers for faults
       if (X86) # decode-bad is x86-only
         # Do not cap the trace size (done to shorten tests) b/c it will then miss