i#4328 AArch64 prefetch and flush instrs: Add trace types for prefetch instructions

clients/drcachesim/CMakeLists.txt

@@ -220,6 +220,15 @@ target_link_libraries(histogram_launcher drmemtrace_analyzer drmemtrace_histogra
   drfrontendlib)
 use_DynamoRIO_extension(histogram_launcher droption)
 add_dependencies(histogram_launcher api_headers)
+
+add_executable(prefetch_analyzer_launcher
+  tests/prefetch_analyzer_launcher.cpp
+  tests/prefetch_analyzer.cpp
+  )
+target_link_libraries(prefetch_analyzer_launcher drmemtrace_analyzer drfrontendlib)
+use_DynamoRIO_extension(prefetch_analyzer_launcher droption)
+add_dependencies(prefetch_analyzer_launcher api_headers)
+
 # We have a companion test built using a separate --build-and-test CMake project in
 # tests/analyzer_separate.cpp to better test 3rd-party usage.
 set_property(GLOBAL PROPERTY DynamoRIO_drmemtrace_src_dir
@@ -248,6 +257,7 @@ endif ()
 if (ZLIB_FOUND)
   target_link_libraries(drcachesim ${ZLIB_LIBRARIES})
   target_link_libraries(histogram_launcher ${ZLIB_LIBRARIES})
+  target_link_libraries(prefetch_analyzer_launcher ${ZLIB_LIBRARIES})
   target_link_libraries(drmemtrace_raw2trace ${ZLIB_LIBRARIES})
   if (NOT AARCH64 AND NOT APPLE)
     target_link_libraries(opcode_mix_launcher ${ZLIB_LIBRARIES})
@@ -326,6 +336,7 @@ endmacro()
 restore_nonclient_flags(drcachesim)
 restore_nonclient_flags(drraw2trace)
 restore_nonclient_flags(histogram_launcher)
+restore_nonclient_flags(prefetch_analyzer_launcher)
 if (NOT AARCH64 AND NOT APPLE)
   restore_nonclient_flags(opcode_mix_launcher)
 endif ()
@@ -369,6 +380,7 @@ endmacro ()
 add_win32_flags(drcachesim)
 add_win32_flags(drraw2trace)
 add_win32_flags(histogram_launcher)
+add_win32_flags(prefetch_analyzer_launcher)
 add_win32_flags(drmemtrace_raw2trace)
 if (NOT AARCH64 AND NOT APPLE)
   add_win32_flags(opcode_mix_launcher)

clients/drcachesim/common/trace_entry.cpp

@@ -36,9 +36,9 @@ const char *const trace_type_names[] = {
     "read",
     "write",
     "prefetch",
-    "prefetcht0",
-    "prefetcht1",
-    "prefetcht2",
+    "prefetch_read_l1",
+    "prefetch_read_l2",
+    "prefetch_read_l3",
     "prefetchnta",
     "prefetch_read",
     "prefetch_write",
@@ -65,4 +65,19 @@ const char *const trace_type_names[] = {
     "non-fetched instr",
     "maybe-fetched instr",
     "sysenter",
+    "prefetch_read_l1_nt",
+    "prefetch_read_l2_nt",
+    "prefetch_read_l3_nt",
+    "prefetch_instr_l1",
+    "prefetch_instr_l1_nt",
+    "prefetch_instr_l2",
+    "prefetch_instr_l2_nt",
+    "prefetch_instr_l3",
+    "prefetch_instr_l3_nt",
+    "prefetch_write_l1",
+    "prefetch_write_l1_nt",
+    "prefetch_write_l2",
+    "prefetch_write_l2_nt",
+    "prefetch_write_l3",
+    "prefetch_write_l3_nt",
 };

clients/drcachesim/common/trace_entry.h

@@ -71,12 +71,22 @@ typedef enum {
     TRACE_TYPE_READ,  /**< A data load. */
     TRACE_TYPE_WRITE, /**< A data store. */
 
-    TRACE_TYPE_PREFETCH, /**< A general prefetch to the level 1 data cache. */
+    TRACE_TYPE_PREFETCH, /**< A general prefetch. */
+
     // X86 specific prefetch
-    TRACE_TYPE_PREFETCHT0,  /**< An x86 prefetch to all levels of the cache. */
-    TRACE_TYPE_PREFETCHT1,  /**< An x86 prefetch to level 1 of the cache. */
-    TRACE_TYPE_PREFETCHT2,  /**< An x86 prefetch to level 2 of the cache. */
+    TRACE_TYPE_PREFETCHT0, /**< An x86 prefetch to all levels of the cache. */
+    TRACE_TYPE_PREFETCH_READ_L1 =
+        TRACE_TYPE_PREFETCHT0, /**< Load prefetch to L1 cache. */
+    TRACE_TYPE_PREFETCHT1,     /**< An x86 prefetch to level 2 cache and higher. */
+    TRACE_TYPE_PREFETCH_READ_L2 =
+        TRACE_TYPE_PREFETCHT1, /**< Load prefetch to L2 cache. */
+    TRACE_TYPE_PREFETCHT2,     /**< An x86 prefetch to level 3 cache and higher. */
+    TRACE_TYPE_PREFETCH_READ_L3 =
+        TRACE_TYPE_PREFETCHT2, /**< Load prefetch to L3 cache. */
+    // This prefetches data into a non-temporal cache structure and into a location
+    // close to the processor, minimizing cache pollution.
     TRACE_TYPE_PREFETCHNTA, /**< An x86 non-temporal prefetch. */
+
     // ARM specific prefetch
     TRACE_TYPE_PREFETCH_READ,  /**< An ARM load prefetch. */
     TRACE_TYPE_PREFETCH_WRITE, /**< An ARM store prefetch. */
@@ -163,6 +173,25 @@ typedef enum {
      */
     TRACE_TYPE_INSTR_SYSENTER,
 
+    // Architecture-agnostic trace entry types for prefetch instructions.
+    TRACE_TYPE_PREFETCH_READ_L1_NT, /**< Non-temporal load prefetch to L1 cache. */
+    TRACE_TYPE_PREFETCH_READ_L2_NT, /**< Non-temporal load prefetch to L2 cache. */
+    TRACE_TYPE_PREFETCH_READ_L3_NT, /**< Non-temporal load prefetch to L3 cache. */
+
+    TRACE_TYPE_PREFETCH_INSTR_L1,    /**< Instr prefetch to L1 cache. */
+    TRACE_TYPE_PREFETCH_INSTR_L1_NT, /**< Non-temporal instr prefetch to L1 cache. */
+    TRACE_TYPE_PREFETCH_INSTR_L2,    /**< Instr prefetch to L2 cache. */
+    TRACE_TYPE_PREFETCH_INSTR_L2_NT, /**< Non-temporal instr prefetch to L2 cache. */
+    TRACE_TYPE_PREFETCH_INSTR_L3,    /**< Instr prefetch to L3 cache. */
+    TRACE_TYPE_PREFETCH_INSTR_L3_NT, /**< Non-temporal instr prefetch to L3 cache. */
+
+    TRACE_TYPE_PREFETCH_WRITE_L1,    /**< Store prefetch to L1 cache. */
+    TRACE_TYPE_PREFETCH_WRITE_L1_NT, /**< Non-temporal store prefetch to L1 cache. */
+    TRACE_TYPE_PREFETCH_WRITE_L2,    /**< Store prefetch to L2 cache. */
+    TRACE_TYPE_PREFETCH_WRITE_L2_NT, /**< Non-temporal store prefetch to L2 cache. */
+    TRACE_TYPE_PREFETCH_WRITE_L3,    /**< Store prefetch to L3 cache. */
+    TRACE_TYPE_PREFETCH_WRITE_L3_NT, /**< Non-temporal store prefetch to L3 cache. */
+
     // Update trace_type_names[] when adding here.
 } trace_type_t;
 
@@ -277,6 +306,8 @@ static inline bool
 type_is_prefetch(const trace_type_t type)
 {
     return (type >= TRACE_TYPE_PREFETCH && type <= TRACE_TYPE_PREFETCH_INSTR) ||
+        (type >= TRACE_TYPE_PREFETCH_READ_L1_NT &&
+         type <= TRACE_TYPE_PREFETCH_WRITE_L3_NT) ||
         type == TRACE_TYPE_HARDWARE_PREFETCH;
 }
 

clients/drcachesim/reader/reader.cpp

@@ -71,13 +71,28 @@ reader_t::operator++()
         case TRACE_TYPE_READ:
         case TRACE_TYPE_WRITE:
         case TRACE_TYPE_PREFETCH:
-        case TRACE_TYPE_PREFETCHT0:
-        case TRACE_TYPE_PREFETCHT1:
-        case TRACE_TYPE_PREFETCHT2:
+        case TRACE_TYPE_PREFETCH_READ_L1:
+        case TRACE_TYPE_PREFETCH_READ_L2:
+        case TRACE_TYPE_PREFETCH_READ_L3:
         case TRACE_TYPE_PREFETCHNTA:
         case TRACE_TYPE_PREFETCH_READ:
         case TRACE_TYPE_PREFETCH_WRITE:
         case TRACE_TYPE_PREFETCH_INSTR:
+        case TRACE_TYPE_PREFETCH_READ_L1_NT:
+        case TRACE_TYPE_PREFETCH_READ_L2_NT:
+        case TRACE_TYPE_PREFETCH_READ_L3_NT:
+        case TRACE_TYPE_PREFETCH_INSTR_L1:
+        case TRACE_TYPE_PREFETCH_INSTR_L1_NT:
+        case TRACE_TYPE_PREFETCH_INSTR_L2:
+        case TRACE_TYPE_PREFETCH_INSTR_L2_NT:
+        case TRACE_TYPE_PREFETCH_INSTR_L3:
+        case TRACE_TYPE_PREFETCH_INSTR_L3_NT:
+        case TRACE_TYPE_PREFETCH_WRITE_L1:
+        case TRACE_TYPE_PREFETCH_WRITE_L1_NT:
+        case TRACE_TYPE_PREFETCH_WRITE_L2:
+        case TRACE_TYPE_PREFETCH_WRITE_L2_NT:
+        case TRACE_TYPE_PREFETCH_WRITE_L3:
+        case TRACE_TYPE_PREFETCH_WRITE_L3_NT:
             have_memref = true;
             assert(cur_tid_ != 0 && cur_pid_ != 0);
             cur_ref_.data.pid = cur_pid_;

clients/drcachesim/tests/allasm-aarch64-prefetch-basic-counts.templatex

@@ -0,0 +1,32 @@
+Hello, world!
+---- <application exited with code 0> ----
+Basic counts tool results:
+Total counts:
+          96 total \(fetched\) instructions
+          96 total unique \(fetched\) instructions
+           0 total non-fetched instructions
+          81 total prefetches
+     .* total data loads
+     .* total data stores
+           1 total threads
+     .* total scheduling markers
+     .* total transfer markers
+     .* total function id markers
+     .* total function return address markers
+     .* total function argument markers
+     .* total function return value markers
+     .* total other markers
+Thread .* counts:
+          96 \(fetched\) instructions
+          96 unique \(fetched\) instructions
+           0 non-fetched instructions
+          81 prefetches
+     .* data loads
+     .* data stores
+     .* scheduling markers
+     .* transfer markers
+     .* function id markers
+     .* function return address markers
+     .* function argument markers
+     .* function return value markers
+     .* other markers

clients/drcachesim/tests/allasm_aarch64_prefetch.asm

@@ -0,0 +1,179 @@
+/* **********************************************************
+ * Copyright (c) 2020 Google, Inc. All rights reserved.
+ * Copyright (c) 2016 ARM Limited. All rights reserved.
+ * **********************************************************/
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ *   this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ *   this list of conditions and the following disclaimer in the documentation
+ *   and/or other materials provided with the distribution.
+ *
+ * * Neither the name of ARM Limited nor the names of its contributors may be
+ *   used to endorse or promote products derived from this software without
+ *   specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL ARM LIMITED OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+        .global  _start
+
+        .align   6
+_start:
+        // Align stack pointer and get some space.
+        mov      x0, sp
+        bic      x0, x0, #63
+        mov      x1, x0        // x1 is top of region
+        sub      x0, x0, #1024 // x0 is bottom of region
+        mov      sp, x0
+
+
+        adr      x0, helloworld
+        adr      x1, .
+
+        // prefetch_read_l1
+        prfm     pldl1keep, [x0]
+        prfum    pldl1keep, [x0]
+
+        // prefetch_read_l1_nt
+        prfm     pldl1strm, [x0]
+        prfum    pldl1strm, [x0]
+        prfum    pldl1strm, [x0]
+
+        // prefetch_read_l2
+        prfm     pldl2keep, [x0]
+        prfum    pldl2keep, [x0]
+        prfm     pldl2keep, [x0]
+        prfum    pldl2keep, [x0]
+
+        // prefetch_read_l2_nt
+        prfm     pldl2strm, [x0]
+        prfm     pldl2strm, [x0]
+        prfum    pldl2strm, [x0]
+        prfum    pldl2strm, [x0]
+        prfum    pldl2strm, [x0]
+
+        // prefetch_read_l3
+        prfm     pldl3keep, [x0]
+        prfm     pldl3keep, [x0]
+        prfm     pldl3keep, [x0]
+        prfum    pldl3keep, [x0]
+        prfum    pldl3keep, [x0]
+        prfum    pldl3keep, [x0]
+
+        // prefetch_read_l3_nt
+        prfm     pldl3strm, [x0]
+        prfm     pldl3strm, [x0]
+        prfm     pldl3strm, [x0]
+        prfm     pldl3strm, [x0]
+        prfum    pldl3strm, [x0]
+        prfum    pldl3strm, [x0]
+        prfum    pldl3strm, [x0]
+
+        // prefetch_instr_l1
+        prfm     plil1keep, [x0]
+        prfm     plil1keep, [x0]
+        prfm     plil1keep, [x0]
+        prfum    plil1keep, [x0]
+        prfum    plil1keep, [x0]
+        prfum    plil1keep, [x0]
+        prfum    plil1keep, [x0]
+
+        // prefetch_instr_l1_nt
+        prfm     plil1strm, [x0]
+        prfm     plil1strm, [x0]
+        prfm     plil1strm, [x0]
+        prfum    plil1strm, [x0]
+        prfum    plil1strm, [x0]
+        prfum    plil1strm, [x0]
+
+        // prefetch_instr_l2
+        prfm     plil2keep, [x0]
+        prfm     plil2keep, [x0]
+        prfm     plil2keep, [x0]
+        prfum    plil2keep, [x0]
+        prfum    plil2keep, [x0]
+
+        // prefetch_instr_l2_nt
+        prfm     plil2strm, [x0]
+        prfm     plil2strm, [x0]
+        prfum    plil2strm, [x0]
+        prfum    plil2strm, [x0]
+
+        // prefetch_instr_l3
+        prfm     plil3keep, [x0]
+        prfum    plil3keep, [x0]
+        prfum    plil3keep, [x0]
+
+        // prefetch_instr_l3_nt
+        prfm     plil3strm, [x0]
+        prfum    plil3strm, [x0]
+
+        // prefetch_write_l1
+        prfm     pstl1keep, [x1]
+        prfm     pstl1keep, [x1]
+        prfum    pstl1keep, [x1]
+        prfum    pstl1keep, [x1]
+        prfum    pstl1keep, [x1]
+
+        // prefetch_write_l1_nt
+        prfm     pstl1strm, [x1]
+        prfm     pstl1strm, [x1]
+        prfum    pstl1strm, [x1]
+        prfum    pstl1strm, [x1]
+
+        // prefetch_write_l2
+        prfm     pstl2keep, [x1]
+        prfm     pstl2keep, [x1]
+        prfum    pstl2keep, [x1]
+
+        // prefetch_write_l2_nt
+        prfm     pstl2strm, [x1]
+        prfum    pstl2strm, [x1]
+
+        // prefetch_write_l3
+        prfm     pstl3keep, [x1]
+        prfm     pstl3keep, [x1]
+        prfm     pstl3keep, [x1]
+        prfum    pstl3keep, [x1]
+        prfum    pstl3keep, [x1]
+        prfum    pstl3keep, [x1]
+        prfum    pstl3keep, [x1]
+
+        // prefetch_write_l3_nt
+        prfm     pstl3strm, [x1]
+        prfm     pstl3strm, [x1]
+        prfm     pstl3strm, [x1]
+        prfum    pstl3strm, [x1]
+        prfum    pstl3strm, [x1]
+        prfum    pstl3strm, [x1]
+
+        // Exit.
+        mov      w0, #1            // stdout
+        adr      x1, helloworld
+        mov      w2, #14           // sizeof(helloworld)
+        mov      w8, #64           // SYS_write
+        svc      #0
+        mov      w0, #0            // status
+        mov      w8, #94           // SYS_exit_group
+        svc      #0
+
+        .data
+        .align   6
+helloworld:
+        .ascii   "Hello, world!\n"