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feat: Update RAM/ROM memory records for new block structure (#4806)
The 4th wire of RAM/ROM read/write gates is generated at proving time as a linear combination of the first three wires scaled by powers of a challenge. To know on which rows to perform this calculation, we must store the indices of read/write gates in the proving key. Previously, these indices were set in the builder based on num_gates, then offset later in the composer to account for the fact that public inputs and/or ecc op gates are placed at the top of the trace. This PR updates this model to work with the new block structure in the builders. In particular, in the builder we set the gate index of ram/rom read/writes based on the row within the block. (Currently ram/rom gates are added to `main`, eventually they'll be in `aux`). Then, we get the correct execution trace row index by later offsetting these values based on the offset at which the black containing these gates is placed in the trace. The method for performing this offset has been moved to execution_trace.hpp since it fundamentally depends on the ordering of the execution trace. Note: This is one step towards getting RAM/ROM to work with the new block structure. It will also be necessary to remove the interleaving of arithmetic gates into read/write gates. This will come in a follow on.
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