RTL Design Blocks: Basic to Advance

Table of Contents

• Features
• Folder Structure
• Python Scripts
  • rtl_scripts
  • iv_scripts
  • veri_scripts
  • vivado_scripts
  • clean_scripts
• Ongoing list of design examples

Features

• RTL Design Blocks: Modular designs for various digital logic components.
• Simulation Support: The designs are compatible with
  • Vivado : Industry-standard for FPGA design and verification.
  • Verilator: High-performance Verilog simulator.
  • Icarus Verilog: Open-source Verilog simulator.
  • GTKwave: Waveform viewer for debugging and analysis.
• Automation: Python_Scripts to streamline the design, simulation, and verification workflows.

Folder Structure

The repository is organized to facilitate efficient RTL design and simulation processes. Below is a breakdown of the folder structure and its contents:

RTL
.
├── doc
├── README.org
├── rtl_designs
│   ├── adder_subtractor
│   ├── always_at_comb
│          ... 
│          ...
│          ...
│
├── rtl_tcl_scripts
│   └── rtl_run.tcl
└── rtl_templates
    ├── design.sv
    ├── interface.sv
    ├── package.svh
    └── tb_design.sv

1. doc: This folder contains documentation files that provide detailed descriptions of the repository’s components, usage guidelines, and design methodologies.
2. README.org: The main entry point for understanding the repository, this file contains an overview, instructions, and helpful tips for using the designs and scripts.
3. rtl_designs: Contains the core RTL design blocks implemented in Verilog and SystemVerilog. Each subfolder represents a specific design modules.
4. rtl_tcl_scripts: Contains TCL scripts for automating tasks such as synthesis, simulation, and verification in Vivado. ==rtl_run.tcl==: A script to automate the execution of design and simulation flows.
5. rtl_templates: Provides templates for quickly starting new RTL design and testbench files, ensuring consistency across the repository:
   • design.sv: Template for creating SystemVerilog design modules.
   • interface.sv: Template for defining SystemVerilog interfaces.
   • package.svh: Template for defining SystemVerilog packages for parameterized designs.
   • tb_design.sv: Template for creating testbenches for verifying RTL modules.

Python Scripts

The Python_Scripts repository includes several Python scripts that automate and simplify the design and simulation processes for various tools. These scripts are used to automate repetative tasks such project creation, simulation, etc. The folder stucture is shown below:

Python_Scripts
.
├── clean_scripts
│   └── clean_all.py
├── iv_scripts
│   ├── archived
│   ├── iv_clean.py
│   └── iv_run.py
├── rtl_scripts
│   └── rtl_design.py
├── sv_scripts
│   ├── sv_clean.py
│   ├── sv_cstrs_design.py
│   ├── sv_cstrs_run.py
│   ├── sv_design.py
│   └── sv_run.py
├── uvm_scripts
│   ├── uvm_clean.py
│   └── uvm_run.py
├── veri_scripts
│   ├── config.vlt
│   ├── veri_clean.py
│   └── veri_run.py
└── vivado_scripts
    ├── vivado_clean.py
    └── vivado_run.py

A detailed description of all the automation scripts can be found here.

For streamlining ==RTL design and simulation==, following scripts are utilized:

rtl_scripts

• Purpose: Automates the creation of RTL design and testbench files. Ensures consistency in design and testbench structure by leveraging predefined templates.
• rtl_design.py: Creates a new folder in the rtl_designs directory.Generates design and testbench files using templates from the rtl_templates directory.

iv_scripts

• Purpose: Facilitates simulation and cleanup when using Icarus Verilog. Automates Icarus Verilog-based design workflows for efficient simulation and cleanup.
• iv_run.py: Simulates the RTL design using Icarus Verilog.
• iv_clean.py: Removes all files generated during the Icarus Verilog simulation, such as .vvp and .vcd files.

veri_scripts

• Purpose: Manages the simulation process using Verilator and provides a seamless Verilator simulation and cleanup workflow.
• veri_run.py: Simulates the RTL design using Verilator.
• veri_clean.py: Cleans up all files and directories generated during Verilator simulations.
• config.vlt: The ==config.vlt== file in Verilator customizes simulation settings and overrides default behaviors.

vivado_scripts

• Purpose: Integrates Vivado TCL scripting for project creation and simulation.
• vivado_run.py: Invokes the rtl_run.tcl script from the rtl_tcl_script folder to create and simulate a Vivado project.
• vivado_clean.py: Removes Vivado-generated project files, logs, and other artifacts.

clean_scripts

• Purpose: General cleanup utility for removing simulation files and logs across all tools. Simplifies maintaining a clean working environment.
• clean_all.py: Deletes all files, logs, and project directories created by various tools (e.g., Icarus Verilog, Verilator, and Vivado).

These scripts collectively enhance productivity by automating repetitive tasks, ensuring consistency, and providing efficient workflows for RTL design and simulation using Icarus Verilog, Verilator, and Vivado.

Ongoing list of design examples

• Adder Subtractor
• Always@(*) and Always_Comb
• APB Protocol
• Assign and If-Else Statement
• Asynchronous FIFO
• Asynchrnous Reset
• Barrel Shifter
• Blocking & Non-Blocking Assignment
• Casex and Casez
• Clock Gating
• Code Converter
• Comparator
• D-FF with Enable
• Decoder
• De-Multiplexer
• Difference between ‘==’ and ‘===’
• Edge Detector
• Encoder
• Even Parity
• Fibonacci
• Flow Control Register
• Frequency Divider
• FSM: Dual Edge Detector
• FSM: Positive Edge Detector
• FSM: Sequence detector
• Full Adder
• Half Adder
• I2C Protocol
• Latch
• Linear Feedback Shift Register
• Mod-N Counter
• Multiplexer
• MUX: Basic Gates
• Pulse Width Modulator
• Race Condition
• Register File
• Register
• Ring Counter
• ROM
• Shift Register
• Signed Magnitude Adder
• SPI
• Synchronus FIFO
• UART
• Universal Counter
• Universal Shift Register
• Up/Down Counter
• Valid-Ready