I am currently a Ph.D. candidate at Wright State University, working as a Graduate Research Assistant in the Digital Receiver Lab. My doctoral research focuses on hardware optimization of the Fast Fourier Transform (FFT) for the Xilinx Zynq UltraScale+ RFSoC 1275 FPGA, aiming for efficient multiple signal detection in military applications and addressing challenges related to computation complexity and signal resolution.
🔬 Know more about my research.
Check out my GitHub repositories for a mix of cool projects.
- 📁 RTL: This GitHub repository features RTL designs from basic to advanced level that are simulated using Verilator, Icarus Verilog or Vivado and GTKwave for visualizing simulated output.
- 📁 SV: This is a repository showcasing advanced verification methodologies using SystemVerilog, including functional verification, testbench creation, and assertion-based verification techniques.
- 📁 UVM: A repository showcasing verification methodologies using the UVM (Universal Verification Methodology) framework, featuring examples for various designs and protocols.
- 📁 VanillaFPRO: Serves for a basic understanding of a SoC design with a memory-mapped I/O subsystem. This repository is heavily inspired from the book FPGA Prototyping by SystemVerilog Examples. The SoC prototyping is conducted on the Zybo-Z7 development board.
- 📁 ZyboZ7: This repository features design examples that are implemented on Xilinx Zynq-7000 SoC series FPGA developed by Digilent called Zybo-Z7.
