loongarch: fixes and other cleanup for portability (#171)

Correct a typo on the floating registers saved during "enter"

While at it, add unimplemented functions for atomics, update
`sljit_cmp_info` to correctly reflect the FPU capabilities and
fix other minor style issues.

Makefile

@@ -40,7 +40,7 @@ SLJIT_LIR_FILES = $(SRCDIR)/sljitLir.c $(SRCDIR)/sljitUtils.c \
 	$(SRCDIR)/sljitNativeMIPS_common.c $(SRCDIR)/sljitNativeMIPS_32.c $(SRCDIR)/sljitNativeMIPS_64.c \
 	$(SRCDIR)/sljitNativePPC_common.c $(SRCDIR)/sljitNativePPC_32.c $(SRCDIR)/sljitNativePPC_64.c \
 	$(SRCDIR)/sljitNativeRISCV_common.c $(SRCDIR)/sljitNativeRISCV_32.c $(SRCDIR)/sljitNativeRISCV_64.c \
-	$(SRCDIR)/sljitNativeS390X.c \
+	$(SRCDIR)/sljitNativeS390X.c $(SRCDIR)/sljitNativeLOONGARCH_64.c \
 	$(SRCDIR)/sljitNativeX86_common.c $(SRCDIR)/sljitNativeX86_32.c $(SRCDIR)/sljitNativeX86_64.c
 
 .PHONY: all clean examples

README

@@ -35,6 +35,7 @@ Special thanks:
   Marc Mutz
   Martin Storsjö
   Michael McConville
+  Mingtao Zhou (LoongArch support)
   Walter Lee
   Wen Xichang
   YunQiang Su

doc/overview.txt

@@ -9,7 +9,7 @@ with SLJIT. Further details can be found in sljitLir.h.
 SLJIT is a platform independent assembler which
   - provides access to common CPU features
   - can be easily ported to wide-spread CPU
-    architectures (e.g. x86, ARM, POWER, MIPS, SPARC, s390x)
+    architectures (e.g. x86, ARM, POWER, MIPS, s390x, LoongArch)
 
 The key challenge of this project is finding a common
 subset of CPU features which
@@ -127,7 +127,7 @@ following rules were introduced:
   - Status flags cannot be controlled directly
     (there are no set/clear/invert operations)
 
-The last two rules allows efficent mapping of status flags.
+The last two rules allows efficient mapping of status flags.
 For example the arithmetic and multiply overflow flag is
 mapped to the same overflow flag bit on x86. This is allowed,
 since no instruction can set both of these flags. When