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soc: openisa_rv32m1: Update target architecture for GCC 12 #48526

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stephanosio
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@stephanosio stephanosio commented Aug 1, 2022

This commit updates the custom target architecture type specified for
the SOC_OPENISA_RV32M1_RI5CY and SOC_OPENISA_RV32M1_ZERO_RISCY SoC
types to be compatible with the GCC 12, which now uses the ISA spec
20191213 by default.

Note that the hack overriding the build system-default -march flag
for these SoCs needs to be removed and they should be properly
specified using the ISA extension Kconfigs.

Signed-off-by: Stephanos Ioannidis [email protected]

NOTE: To be merged after Zephyr SDK 0.15.0 is mainlined.

This commit updates the custom target architecture type specified for
the `SOC_OPENISA_RV32M1_RI5CY` and `SOC_OPENISA_RV32M1_ZERO_RISCY` SoC
types to be compatible with the GCC 12, which now uses the ISA spec
20191213 by default.

Note that the hack overriding the build system-default `-march` flag
for these SoCs needs to be removed and they should be properly
specified using the ISA extension Kconfigs.

Signed-off-by: Stephanos Ioannidis <[email protected]>
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@carlocaione carlocaione left a comment

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:( LGTM but ugly

@mbolivar-nordic
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I'm not touching this board anymore; I upstreamed support for it as a contract worker at a previous job, and studiously avoided volunteering to maintain it ;).

@stephanosio stephanosio marked this pull request as ready for review August 25, 2022 13:39
@stephanosio stephanosio requested a review from dleach02 as a code owner August 25, 2022 13:39
@zephyrbot zephyrbot added the area: RISCV RISCV Architecture (32-bit & 64-bit) label Aug 25, 2022
@stephanosio
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To be merged as part of #49496

@stephanosio stephanosio added the DNM This PR should not be merged (Do Not Merge) label Aug 25, 2022
@stephanosio
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Merged as part of #49496

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6 participants