soc: arm: nxp_s32: s32k1: unselect CPU_HAS_xCACHE

Following changes in #64978, align CPU_HAS_xCACHE symbols with the CMSIS feature definitions in the device headers so that both have the same value. Fixes #66147 Signed-off-by: Manuel Argüelles <[email protected]>
zephyrproject-rtos · Dec 5, 2023 · 673f38f · 673f38f
1 parent 3d3b287
commit 673f38f
Showing 1 changed file with 0 additions and 12 deletions.
diff --git a/soc/arm/nxp_s32/s32k1/Kconfig.soc b/soc/arm/nxp_s32/s32k1/Kconfig.soc
@@ -20,48 +20,36 @@ config SOC_S32K142
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
-	select CPU_HAS_DCACHE
-	select CPU_HAS_ICACHE
 
 config SOC_S32K142W
 	bool "S32K142W"
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
-	select CPU_HAS_DCACHE
-	select CPU_HAS_ICACHE
 
 config SOC_S32K144
 	bool "S32K144"
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
-	select CPU_HAS_DCACHE
-	select CPU_HAS_ICACHE
 
 config SOC_S32K144W
 	bool "S32K144W"
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
-	select CPU_HAS_DCACHE
-	select CPU_HAS_ICACHE
 
 config SOC_S32K146
 	bool "S32K146"
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
-	select CPU_HAS_DCACHE
-	select CPU_HAS_ICACHE
 
 config SOC_S32K148
 	bool "S32K148"
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
-	select CPU_HAS_DCACHE
-	select CPU_HAS_ICACHE
 
 endchoice