cmd/compile: clean up PPC64.rules typed aux changes

This adds a few minor changes from the first review. Passes toolstash-check Change-Id: I00f6f1b0235d0a8c686aa8793d0473b8fc6b1495 Reviewed-on: https://go-review.googlesource.com/c/go/+/229699 Run-TryBot: Lynn Boger <[email protected]> Reviewed-by: Keith Randall <[email protected]>
xujianhai666 · May 21, 2020 · bbd7f83 · bbd7f83
1 parent 677acfe
commit bbd7f83
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Showing 2 changed files with 84 additions and 84 deletions.
diff --git a/src/cmd/compile/internal/ssa/gen/PPC64.rules b/src/cmd/compile/internal/ssa/gen/PPC64.rules
@@ -275,8 +275,8 @@
 (ISEL [0] (ANDconst [d] y) (MOVDconst [-1]) (CMPUconst [c] (ANDconst [d] y))) && c >= d => (ANDconst [d] y)
 (ORN x (MOVDconst [-1])) => x
 
-(ADDconstForCarry [c] (MOVDconst [d])) && c < 0 && (int64(c) <  0 || int64(c) + d >= 0) => (FlagCarryClear)
-(ADDconstForCarry [c] (MOVDconst [d])) && c < 0 &&  int64(c) >= 0 && int64(c) + d <  0  => (FlagCarrySet)
+(ADDconstForCarry [c] (MOVDconst [d])) && c < 0 && (c <  0 || int64(c) + d >= 0) => (FlagCarryClear)
+(ADDconstForCarry [c] (MOVDconst [d])) && c < 0 &&  c >= 0 && int64(c) + d <  0  => (FlagCarrySet)
 
 (MaskIfNotCarry (FlagCarrySet)) => (MOVDconst [0])
 (MaskIfNotCarry (FlagCarryClear)) => (MOVDconst [-1])
@@ -802,48 +802,48 @@
 // the temp register. So don't fold address of global, unless there
 // is only one use.
 (MOVBstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) =>
         (MOVBstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
 (MOVHstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) =>
         (MOVHstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
 (MOVWstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) =>
         (MOVWstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
 (MOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 =>
         (MOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
 
 (FMOVSstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) =>
         (FMOVSstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
 (FMOVDstore [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) =>
         (FMOVDstore [off1+off2] {mergeSymTyped(sym1,sym2)} ptr val mem)
 
 (MOVBZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) =>
         (MOVBZload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
 (MOVHload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) =>
         (MOVHload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
 (MOVHZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) =>
         (MOVHZload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
 (MOVWload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 =>
         (MOVWload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
 (MOVWZload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) =>
         (MOVWZload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
 (MOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 =>
         (MOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
 (FMOVSload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) =>
         (FMOVSload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
 (FMOVDload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
-	&& (ptr.Op != OpSB || p.Uses == 1) =>
+	&& is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1) =>
         (FMOVDload [off1+off2] {mergeSymTyped(sym1,sym2)} ptr mem)
 
 // Fold offsets for loads.
@@ -893,17 +893,17 @@
 
 // Fold symbols into storezero
 (MOVDstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2)
-	&& (x.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 ->
-    (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem)
+	&& (x.Op != OpSB || p.Uses == 1) && (off1+off2)%4 == 0 =>
+    (MOVDstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} x mem)
 (MOVWstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2)
-	&& (x.Op != OpSB || p.Uses == 1) ->
-    (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem)
+	&& (x.Op != OpSB || p.Uses == 1) =>
+    (MOVWstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} x mem)
 (MOVHstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2)
-	&& (x.Op != OpSB || p.Uses == 1) ->
-    (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem)
+	&& (x.Op != OpSB || p.Uses == 1) =>
+    (MOVHstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} x mem)
 (MOVBstorezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2)
-	&& (x.Op != OpSB || p.Uses == 1) ->
-    (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem)
+	&& (x.Op != OpSB || p.Uses == 1) =>
+    (MOVBstorezero [off1+off2] {mergeSymTyped(sym1,sym2)} x mem)
 
 // atomic intrinsics
 (AtomicLoad(8|32|64|Ptr)  ptr mem) => (LoweredAtomicLoad(8|32|64|Ptr) [1] ptr mem)