##Coumputer Architecture ###MIPS PIPELINED CPU
ZJU CA 2015
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Lab1 Single Cycle MIPS CPU, the controller module has redundance.
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Lab2 Pipelined CPU with hazards, using new structure on top & controller.
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Lab3 Pipelined CPU with stalls. (in a mess)
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Lab4 Pipelined CPU Add forwarding. (using new structure)