uarths recv intr worked after sbi_putc(0)

wyfcyx · Aug 3, 2020 · be22c1d · be22c1d
1 parent ba4dd90
commit be22c1d
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Showing 3 changed files with 9 additions and 4 deletions.
diff --git a/os/built/opensbi.bin b/os/built/opensbi.bin
diff --git a/os/src/interrupt/handler.rs b/os/src/interrupt/handler.rs
@@ -3,6 +3,7 @@ use super::timer;
 use riscv::register::stvec;
 use riscv::register::scause::Scause;
 use riscv::register::scause::{Exception, Trap, Interrupt};
+use crate::sbi::console_putchar;
 
 global_asm!(include_str!("./interrupt.asm"));
 
@@ -28,7 +29,7 @@ pub fn handle_interrupt(context: &mut Context, scause: Scause, stval: usize) {
         Trap::Exception(Exception::Breakpoint) => breakpoint(context),
         // 时钟中断
         Trap::Interrupt(Interrupt::SupervisorTimer) => supervisor_timer(context),
-        Trap::Interrupt(Interrupt::SupervisorSoft) => supervisor_soft(context),
+        Trap::Interrupt(Interrupt::SupervisorSoft) => supervisor_soft(context, stval),
         // 其他情况，终止当前线程
         _ => fault(context, scause, stval),
     }
@@ -43,8 +44,10 @@ fn supervisor_timer(_: &Context) {
     timer::tick();
 }
 
-fn supervisor_soft(_: &Context) {
-    println!("soft");
+fn supervisor_soft(_: &Context, stval: usize) {
+    //panic!("into ssoft");
+    //println!("stval = {}", stval & 0xff);
+    console_putchar(stval & 0xff);
     unsafe {
         let mut sip: usize = 0;
         llvm_asm!("csrci sip, 1 << 1" : "=r"(sip) ::: "volatile");

diff --git a/tools/opensbi/lib/sbi_trap.c b/tools/opensbi/lib/sbi_trap.c
@@ -159,10 +159,12 @@ void sbi_trap_handler(struct sbi_trap_regs *regs, struct sbi_scratch *scratch)
 			unsigned irq_id = *irq_id_ptr;
 			// putchar
 			char c = *(unsigned*)(0x38000004) & 0xff;
-			sbi_printf("%c", c);
+			//sbi_printf("%c", c);
+			sbi_putc(0);
 			// complete
 			*irq_id_ptr = irq_id;
 
+			csr_write(CSR_STVAL, c);
 			csr_set(CSR_MIP, MIP_SSIP);
 			break;
 		default: