- Hw2-1 Model Analysis Using Pytorch
- Hw2-2 HW 2-2 Add more statistics to analyze the an ONNX model
- HW2-3 Build tool scripts to manipulate an ONNX model graph
- HW2-4 Using Pytorch C++ API to do model analysis on the transformed model graph
- HW4-1 Mix Adder
- Hw4-2 Add-Suber
- Hw4-3 Booth Multiplier
- Hw4-4 Datapath Implementation
- Hw5-1 TrafficLight with Pedestrian button
- Hw5-2 Calculator
- Hw5-2-1 Negative Integer Generator
- Hw5-2-2 N operands N-1 operators(+、-)
- Hw5-2-3 Order of Operation (+、-、*、(、))
- Hw5-3 LFSR-base 1A2B Number Guess Game
- Hw5-3-1 Pseudo Random Number Generator
- Hw5-3-2 1A2B game quiz
- Hw6-1 費波那契數列 Fibonacci Series
- Hw6-2 C/Assembly Hybrid Programming
- Hw6-3 2x2 Sudoku
- HW 7-1 RISC-V M-Standard Extension
- HW 7-2 RISC-V Bit Manipulation Extension
- Hw 8-1 Instruction Expansion (U-type: Lui)
- Hw 8-2 Single-Cycle CPU Design
- Hw 8-3 Testbench Generator for RV32I Base Instruction
- Hw 9-1 5-stage pipelined CPU Implementation
- Hw 9-2 Data and Control Hazards
- Hw 9-3 Performance Counters and Performance Analysis
- HW 11-1 SoC Integration with CPU
- HW 11-2 Performance Enhancement Using DMA
- HW 11-3 Upgrade AXI Bus Design to Support Burst Model
- HW 11-3-1 Upgrade the AXI Bus Design
- HW 11-3-2 Modify Data memory and DMA controller (Interface) to support AXI Burst Mode.
- Hw 14-1 - Make accelerator move data by itself
- Hw 14-2 - Make the AXI bus support more masters (Accelerator)
- Hw 14-3 Put Everything together to run a different dimension matrix multiplication
- Hw 14-4 Prepare software for the Conv2D operation and compare with the result in Lab 11.
- Group works(Hw9-4, Hw7-2) are not included in this repository.
- Fixes needed:
- hw2-2-3, hw2-4-3 (with minor errors)
- hw2-4, hw5-2-3 (my design is not robust)
- I only uploaded the committed files, not the complete contents of each lab.