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aarch64: int min max (bytecodealliance#161)
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Verify integer min/max.

These rules are a great demonstration of the new priority support, since
the correctness of the `cmp_and_choose` helper rule for `fits_in_64`
relies on the higher priority 16-bit case.

Updates bytecodealliance#128
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mmcloughlin authored Oct 17, 2024
1 parent 42d3566 commit cb203cc
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Showing 4 changed files with 26 additions and 6 deletions.
16 changes: 16 additions & 0 deletions cranelift/codegen/src/inst_specs.isle
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Expand Up @@ -220,3 +220,19 @@
(spec (sextend x)
(match (= result (sign_ext (widthof result) x))))
(instantiate sextend extend)

(spec (smin x y)
(match (= result (if (bvsle x y) x y))))
(instantiate smin bv_binary_8_to_64)

(spec (umin x y)
(match (= result (if (bvule x y) x y))))
(instantiate umin bv_binary_8_to_64)

(spec (smax x y)
(provide (= result (if (bvsge x y) x y))))
(instantiate smax bv_binary_8_to_64)

(spec (umax x y)
(provide (= result (if (bvuge x y) x y))))
(instantiate umax bv_binary_8_to_64)
2 changes: 1 addition & 1 deletion cranelift/codegen/src/isa/aarch64/inst.isle
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Expand Up @@ -2192,7 +2192,7 @@
(extern constructor writable_link_reg writable_link_reg)

(decl writable_zero_reg () WritableReg)
(spec (writable_zero_reg) (provide (= (zero_ext (widthof result) #b0) result)))
(spec (writable_zero_reg) (provide true)) ; zero register is just a write sink
(extern constructor writable_zero_reg writable_zero_reg)

(decl value_regs_zero () ValueRegs)
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13 changes: 8 additions & 5 deletions cranelift/codegen/src/isa/aarch64/lower.isle
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Expand Up @@ -1122,11 +1122,14 @@
;; cmp $x, $y
;; csel .., $x, $y, $cc
(decl cmp_and_choose (Type Cond bool Value Value) ValueRegs)
(rule (cmp_and_choose (fits_in_64 ty) cc _ x y)
(attr cmp_and_choose (veri chain))
(rule cmp_and_choose_64
(cmp_and_choose (fits_in_64 ty) cc _ x y)
(let ((x Reg (put_in_reg x))
(y Reg (put_in_reg y)))
(with_flags_reg (cmp (operand_size ty) x y)
(csel cc x y))))
(attr cmp_and_choose_64 (veri priority))

;; `i16` and `i8` min/max require sign extension as
;; the comparison operates on (at least) 32 bits.
Expand All @@ -1136,13 +1139,13 @@
(with_flags_reg (cmp (operand_size ty) x y)
(csel cc x y))))

(rule 2 (lower (has_type (and (fits_in_64 ty) (ty_int _)) (umin x y)))
(rule umin 2 (lower (has_type (and (fits_in_64 ty) (ty_int _)) (umin x y)))
(cmp_and_choose ty (Cond.Lo) $false x y))
(rule 2 (lower (has_type (and (fits_in_64 ty) (ty_int _)) (smin x y)))
(rule smin 2 (lower (has_type (and (fits_in_64 ty) (ty_int _)) (smin x y)))
(cmp_and_choose ty (Cond.Lt) $true x y))
(rule 2 (lower (has_type (and (fits_in_64 ty) (ty_int _)) (umax x y)))
(rule umax 2 (lower (has_type (and (fits_in_64 ty) (ty_int _)) (umax x y)))
(cmp_and_choose ty (Cond.Hi) $false x y))
(rule 2 (lower (has_type (and (fits_in_64 ty) (ty_int _)) (smax x y)))
(rule smax 2 (lower (has_type (and (fits_in_64 ty) (ty_int _)) (smax x y)))
(cmp_and_choose ty (Cond.Gt) $true x y))

;; Vector types.
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1 change: 1 addition & 0 deletions cranelift/codegen/src/prelude.isle
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Expand Up @@ -638,6 +638,7 @@
;; An extractor that only matches integers.
(decl ty_int (Type) Type)
(extern extractor ty_int ty_int)
(spec (ty_int arg) (provide (= arg result)))

;; An extractor that only matches scalar types, float or int or ref's.
(decl ty_scalar (Type) Type)
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