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minor updates
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@tinebp
tinebp committed Aug 6, 2024
1 parent d276875 commit c265ff9
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Showing 4 changed files with 105 additions and 42 deletions.
1 change: 1 addition & 0 deletions hw/rtl/core/VX_core.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -313,6 +313,7 @@ module VX_core import VX_gpu_pkg::*; #(
.DATA_SIZE (DCACHE_WORD_SIZE),
.TAG_WIDTH (DCACHE_TAG_WIDTH),
.TAG_SEL_BITS (DCACHE_TAG_WIDTH - `UUID_WIDTH),
.ARBITER ("P"),
.REQ_OUT_BUF (0),
.RSP_OUT_BUF (0)
) lsu_adapter (
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1 change: 1 addition & 0 deletions hw/rtl/core/VX_lmem_unit.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -162,6 +162,7 @@ module VX_lmem_unit import VX_gpu_pkg::*; #(
.DATA_SIZE (LSU_WORD_SIZE),
.TAG_WIDTH (LSU_TAG_WIDTH),
.TAG_SEL_BITS (LSU_TAG_WIDTH - `UUID_WIDTH),
.ARBITER ("P"),
.REQ_OUT_BUF (3),
.RSP_OUT_BUF (0)
) lsu_adapter (
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40 changes: 39 additions & 1 deletion hw/rtl/libs/VX_elastic_buffer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,8 @@ module VX_elastic_buffer #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter OUT_REG = 0,
parameter LUTRAM = 0
parameter LUTRAM = 0,
parameter MAX_FANOUT = 0
) (
input wire clk,
input wire reset,
Expand All @@ -40,6 +41,43 @@ module VX_elastic_buffer #(
assign data_out = data_in;
assign ready_in = ready_out;

end else if (MAX_FANOUT != 0 && (DATAW > (MAX_FANOUT + MAX_FANOUT/2))) begin

localparam NUM_SLICES = `CDIV(DATAW, MAX_FANOUT);
localparam N_DATAW = DATAW / NUM_SLICES;

for (genvar i = 0; i < NUM_SLICES; ++i) begin

localparam S_DATAW = (i == NUM_SLICES-1) ? (DATAW - i * N_DATAW) : N_DATAW;

wire valid_out_t, ready_in_t;
`UNUSED_VAR (valid_out_t)
`UNUSED_VAR (ready_in_t)

`RESET_RELAY (slice_reset, reset);

VX_elastic_buffer #(
.DATAW (S_DATAW),
.SIZE (SIZE),
.OUT_REG (OUT_REG),
.LUTRAM (LUTRAM)
) buffer_slice (
.clk (clk),
.reset (slice_reset),
.valid_in (valid_in),
.data_in (data_in[i * N_DATAW +: S_DATAW]),
.ready_in (ready_in_t),
.valid_out (valid_out_t),
.data_out (data_out[i * N_DATAW +: S_DATAW]),
.ready_out (ready_out)
);

if (i == 0) begin
assign ready_in = ready_in_t;
assign valid_out = valid_out_t;
end
end

end else if (SIZE == 1) begin

VX_pipe_buffer #(
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105 changes: 64 additions & 41 deletions hw/rtl/libs/VX_pipe_register.sv
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Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Expand All @@ -14,65 +14,88 @@
`include "VX_platform.vh"

`TRACING_OFF
module VX_pipe_register #(
parameter DATAW = 1,
parameter RESETW = 0,
parameter DEPTH = 1
module VX_pipe_register #(
parameter DATAW = 1,
parameter RESETW = 0,
parameter DEPTH = 1,
parameter MAX_FANOUT = 0
) (
input wire clk,
input wire reset,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
);
if (DEPTH == 0) begin
if (DEPTH == 0) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (enable)
assign data_out = data_in;
end else if (DEPTH == 1) begin
if (RESETW == 0) begin
`UNUSED_VAR (reset)
reg [DATAW-1:0] value;
assign data_out = data_in;
end else if (DEPTH == 1) begin
if (MAX_FANOUT != 0 && (DATAW > (MAX_FANOUT + MAX_FANOUT/2))) begin
localparam NUM_SLICES = `CDIV(DATAW, MAX_FANOUT);
localparam N_DATAW = DATAW / NUM_SLICES;
for (genvar i = 0; i < NUM_SLICES; ++i) begin
localparam SLICE_START = i * N_DATAW;
localparam SLICE_END = SLICE_START + S_DATAW - 1;
localparam S_DATAW = (i == NUM_SLICES-1) ? (DATAW - SLICE_START) : N_DATAW;
localparam S_RESETW = (SLICE_END >= (DATAW - RESETW)) ?
((SLICE_START >= (DATAW - RESETW)) ? S_DATAW : (SLICE_END - (DATAW - RESETW) + 1)) : 0;
VX_pipe_register #(
.DATAW (S_DATAW),
.RESETW (S_RESETW)
) pipe_register_slice (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (data_in[i * N_DATAW +: S_DATAW]),
.data_out (data_out[i * N_DATAW +: S_DATAW])
);
end
end else begin
if (RESETW == 0) begin
`UNUSED_VAR (reset)
reg [DATAW-1:0] value;

always @(posedge clk) begin
if (enable) begin
value <= data_in;
always @(posedge clk) begin
if (enable) begin
value <= data_in;
end
end
end
assign data_out = value;
end else if (RESETW == DATAW) begin
reg [DATAW-1:0] value;
assign data_out = value;
end else if (RESETW == DATAW) begin
reg [DATAW-1:0] value;

always @(posedge clk) begin
if (reset) begin
value <= RESETW'(0);
end else if (enable) begin
value <= data_in;
always @(posedge clk) begin
if (reset) begin
value <= RESETW'(0);
end else if (enable) begin
value <= data_in;
end
end
end
assign data_out = value;
end else begin
reg [DATAW-RESETW-1:0] value_d;
reg [RESETW-1:0] value_r;
assign data_out = value;
end else begin
reg [DATAW-RESETW-1:0] value_d;
reg [RESETW-1:0] value_r;

always @(posedge clk) begin
if (reset) begin
value_r <= RESETW'(0);
end else if (enable) begin
value_r <= data_in[DATAW-1:DATAW-RESETW];
always @(posedge clk) begin
if (reset) begin
value_r <= RESETW'(0);
end else if (enable) begin
value_r <= data_in[DATAW-1:DATAW-RESETW];
end
end
end

always @(posedge clk) begin
if (enable) begin
value_d <= data_in[DATAW-RESETW-1:0];
always @(posedge clk) begin
if (enable) begin
value_d <= data_in[DATAW-RESETW-1:0];
end
end
end
assign data_out = {value_r, value_d};
assign data_out = {value_r, value_d};
end
end
end else begin
wire [DEPTH:0][DATAW-1:0] data_delayed;
wire [DEPTH:0][DATAW-1:0] data_delayed;
assign data_delayed[0] = data_in;
for (genvar i = 1; i <= DEPTH; ++i) begin
VX_pipe_register #(
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