Merge pull request Xilinx#117 from sgrace/2021.1_next

Cleaned up Makefiles
vmayoral · Jul 7, 2021 · c9d251d · c9d251d
2 parents 7fd3905 + 499cf15
commit c9d251d
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Showing 4 changed files with 11 additions and 11 deletions.
diff --git a/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/Makefile b/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/Makefile
@@ -23,7 +23,7 @@ XF_PROJ_ROOT ?= $(shell bash -c 'export MK_PATH=$(MK_PATH); echo $${MK_PATH%/AI_
 # Makefile input options
 TARGET := hw_emu
 PFM := tutorial
-EMU_CMD := ./launch_hw_emu.sh 
+EMU_CMD := ./launch_hw_emu.sh
 
 # File names and locations
 GRAPH := aie/graph.cpp
@@ -60,7 +60,8 @@ LDCLFLAGS :=
 
 GCC_FLAGS := -Wall -c \
 			 -std=c++14 \
-			 -Wno-int-to-pointer-cast
+			 -Wno-int-to-pointer-cast \
+			 --sysroot=${SDKTARGETSYSROOT}
 
 GCC_INCLUDES := -I$(SDKTARGETSYSROOT)/usr/include/xrt \
 				-I$(SDKTARGETSYSROOT)/usr/include \
@@ -70,7 +71,8 @@ GCC_INCLUDES := -I$(SDKTARGETSYSROOT)/usr/include/xrt \
 
 GCC_LIB := -ladf_api_xrt -lxrt_coreutil \
 		   -L$(SDKTARGETSYSROOT)/usr/lib \
-		   -L${XILINX_VITIS}/aietools/lib/aarch64.o
+		   -L${XILINX_VITIS}/aietools/lib/aarch64.o \
+		   --sysroot=${SDKTARGETSYSROOT}
 
 .ONESHELL:
 .PHONY: clean all kernels aie xclbin host package run_emu

diff --git a/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/sw/embedded_exec.sh b/AI_Engine_Development/Design_Tutorials/04-custom-platform-emulation/sw/embedded_exec.sh
@@ -0,0 +1,4 @@
+!/bin/bash
+export XILINX_XRT=/usr
+cd /mnt/sd*1
+./host.exe a.xclbin
diff --git a/AI_Engine_Development/Feature_Tutorials/06-versal-system-design-clocking-tutorial/Makefile b/AI_Engine_Development/Feature_Tutorials/06-versal-system-design-clocking-tutorial/Makefile
@@ -125,9 +125,6 @@ xclbin: guard-PLATFORM_REPO_PATHS $(GRAPH_O) $(KERNEL_XO)
 host: guard-CXX guard-SDKTARGETSYSROOT
 	cd ./sw 
 	$(CXX) $(GCC_FLAGS) $(GCC_INCLUDES) -o aie_control_xrt.o ../Work/ps/c_rts/aie_control_xrt.cpp
-	ifeq (${HOST_ARCH},aarch64)
-		$(CXX) $(GCC_FLAGS) $(GCC_INCLUDES) -o main.o /wrk/vitis_collateral/Jenkins_Infra_Support/06-versal-system-design-clocking/host.cpp
-	endif
 	$(CXX) $(GCC_FLAGS) $(GCC_INCLUDES) -o main.o host.cpp
 	$(CXX) *.o $(GCC_LIB) -std=c++14 -o host.exe 
 	@echo "COMPLETE: Host application created."

diff --git a/AI_Engine_Development/Feature_Tutorials/12-axis-traffic-generator/Makefile b/AI_Engine_Development/Feature_Tutorials/12-axis-traffic-generator/Makefile
@@ -13,7 +13,6 @@
 #limitations under the License.
 #
 
-
 #Check environment setup
 ifndef ROOTFS
   ROOTFS = ${PLATFORM_REPO_PATHS}/sw/versal/xilinx-versal-common-v2021.1/rootfs.ext4
@@ -25,9 +24,7 @@ ifndef IMAGE
 endif
 
 SDKTARGETSYSROOT ?= ${SYSROOT}
-DSPLIB_ROOT := /wrk/vitis_collateral/Jenkins_Infra_Support/xf_dsp
-PYTHONPATH := ${XILINX_VIVADO}/data/emulation/hw_em/lib/python/:${XILINX_VIVADO}/data/emulation/ip_utils/xtlm_ipc/xtlm_ipc_v1_0/python/
-PYTHON := /tools/batonroot/rodin/engkits/lnx64/python-3.6.5_metropolis/bin/python3
+PYTHONPATH += ${XILINX_VIVADO}/data/emulation/hw_em/lib/python/:${XILINX_VIVADO}/data/emulation/ip_utils/xtlm_ipc/xtlm_ipc_v1_0/python/
 
 #DSP LIB Includes
 DSP_KERNEL_HDR         := $(DSPLIB_ROOT)/L1/include/aie
@@ -210,4 +207,4 @@ clean:
 	rm -rf sw/sd_card sw/sd_card.img
 
 run_tgen:
-	python3 sw/pysrc/run_traffic_gen.py	${PLIO_WIDTH} 0
+	python3 sw/pysrc/run_traffic_gen.py	${PLIO_WIDTH} 0