Machine Learning PhD at Georgia Tech | Ex - Chip Design @ TI | IIT Roorkee '19
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Georgia Tech
- Atlanta, GA
Highlights
- Pro
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neuro-galaxy/poyo
neuro-galaxy/poyo PublicOfficial Implementation of POYO-1 https://poyo-brain.github.io/
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veripool/verilog-mode
veripool/verilog-mode PublicVerilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
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Radix-2-FFT
Radix-2-FFT PublicVerilog code for a circuit implementation of Radix-2 FFT
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