Merge pull request #485 from udo-munk/dev

merge dev
udo-munk · Dec 15, 2024 · 430de17 · 430de17
2 parents 1e770fa + 10b67c3
commit 430de17
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diff --git a/.github/workflows/makefile-ubuntu.yml b/.github/workflows/makefile-ubuntu.yml
@@ -15,7 +15,7 @@ jobs:
     - uses: actions/checkout@v4
 
     - name: Install dependencies
-      run: sudo apt install libglu1-mesa-dev
+      run: sudo apt install libjpeg-turbo8-dev libglu1-mesa-dev
 
     - name: Build binaries
       run: make

diff --git a/altairsim/srcsim/Makefile b/altairsim/srcsim/Makefile
@@ -123,8 +123,8 @@ INSTALL_DATA = $(INSTALL) -m 644
 
 # core system source files for the CPU simulation
 CORE_SRCS = sim8080.c simcore.c simdis.c simfun.c simglb.c simice.c simint.c \
-	simmain.c simutil.c simz80.c simz80-cb.c simz80-dd.c simz80-ddcb.c \
-	simz80-ed.c simz80-fd.c simz80-fdcb.c
+	simmain.c simz80.c simz80-cb.c simz80-dd.c simz80-ddcb.c simz80-ed.c \
+	simz80-fd.c simz80-fdcb.c
 SRCS = $(CORE_SRCS) $(MACHINE_SRCS) $(IO_SRCS)
 XXSRCS = $(FP_SRCS)
 OBJS = $(SRCS:.c=.o) $(XXSRCS:.cpp=.o)

diff --git a/altairsim/srcsim/sim.h b/altairsim/srcsim/sim.h
@@ -24,6 +24,7 @@
  * 21-AUG-2018 improved memory configuration
  * 29-AUG-2021 new memory configuration sections
  * 09-MAY-2024 added more defines for conditional compiling components
+ * 14-DEC-2024 added hardware breakpoint support
  */
 
 #ifndef SIM_INC
@@ -38,14 +39,17 @@
 #define CPU_SPEED 2	/* default CPU speed */
 /*#define ALT_I8080*/	/* use alt. 8080 sim. primarily optimized for size */
 /*#define ALT_Z80*/	/* use alt. Z80 sim. primarily optimized for size */
-#define UNDOC_INST	/* compile undocumented instructions */
+#define UNDOC_INST	/* compile undocumented instrs. (required by ALT_*) */
+#ifndef EXCLUDE_Z80
 /*#define FAST_BLOCK*/	/* much faster but not accurate Z80 block instr. */
+#endif
 
 /*#define WANT_ICE*/	/* attach ICE to headless machine */
 #ifdef WANT_ICE
 /*#define WANT_TIM*/	/* don't count t-states */
 /*#define HISIZE  1000*//* no history */
-/*#define SBSIZE  10*/	/* no breakpoints */
+/*#define SBSIZE  10*/	/* no software breakpoints */
+/*#define WANT_HB*/	/* no hardware breakpoint */
 #endif
 
 #define HAS_DAZZLER	/* has simulated I/O for Cromemco Dazzler */

diff --git a/altairsim/srcsim/simcfg.c b/altairsim/srcsim/simcfg.c
@@ -40,7 +40,6 @@
 #include "simdefs.h"
 #include "simglb.h"
 #include "simmem.h"
-#include "simutil.h"
 #include "simcfg.h"
 
 #include "altair-88-sio.h"
@@ -215,7 +214,7 @@ void config(void)
 			} else if (!strcmp(t1, "sio3_baud_rate")) {
 				sio3_baud_rate = atoi(t2);
 			} else if (!strcmp(t1, "fp_port")) {
-				fp_port = (BYTE) exatoi(t2);
+				fp_port = (BYTE) strtol(t2, NULL, 16);
 			} else if (!strcmp(t1, "fp_fps")) {
 #ifdef FRONTPANEL
 				fp_fps = (float) atoi(t2);

diff --git a/altairsim/srcsim/simmem.h b/altairsim/srcsim/simmem.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2016-2021 Udo Munk
  * Copyright (C) 2021 David McNaughton
+ * Copyright (C) 2024 Thomas Eberhardt
  *
  * This module implements memory management for an Altair 8800 system
  *
@@ -17,18 +18,24 @@
  * 04-NOV-2019 add functions for direct memory access
  * 31-JUL-2021 allow building machine without frontpanel
  * 29-AUG-2021 new memory configuration sections
+ * 14-DEC-2024 added hardware breakpoint support
  */
 
 #ifndef SIMMEM_INC
 #define SIMMEM_INC
 
 #include "sim.h"
 #include "simdefs.h"
+#ifdef WANT_ICE
+#include "simice.h"
+#endif
 
 #include "tarbell_fdc.h"
 
-#ifdef FRONTPANEL
+#if defined(FRONTPANEL) || defined(BUS_8080)
 #include "simglb.h"
+#endif
+#ifdef FRONTPANEL
 #include "simctl.h"
 #include "frontpanel.h"
 #endif
@@ -67,6 +74,9 @@ extern void init_memory(void);
 static inline void memwrt(WORD addr, BYTE data)
 {
 #ifdef BUS_8080
+#ifndef FRONTPANEL
+	cpu_bus &= ~CPU_M1;
+#endif
 	cpu_bus &= ~(CPU_WO | CPU_MEMR);
 #endif
 
@@ -77,7 +87,13 @@ static inline void memwrt(WORD addr, BYTE data)
 		fp_led_data = 0xff;
 		fp_sampleData();
 		wait_step();
-	}
+	} else
+		cpu_bus &= ~CPU_M1;
+#endif
+
+#ifdef WANT_HB
+	if (hb_flag && hb_addr == addr && (hb_mode & HB_WRITE))
+		hb_trig = HB_WRITE;
 #endif
 
 	if (p_tab[addr >> 8] == MEM_RW) {
@@ -90,6 +106,18 @@ static inline BYTE memrdr(WORD addr)
 {
 	register BYTE data;
 
+#ifdef WANT_HB
+	if (hb_flag && hb_addr == addr) {
+		if (cpu_bus & CPU_M1) {
+			if (hb_mode & HB_EXEC)
+				hb_trig = HB_EXEC;
+		} else {
+			if (hb_mode & HB_READ)
+				hb_trig = HB_READ;
+		}
+	}
+#endif
+
 	if (tarbell_rom_active && tarbell_rom_enabled) {
 		if (addr <= 0x001f) {
 			data = tarbell_rom[addr];
@@ -108,6 +136,9 @@ static inline BYTE memrdr(WORD addr)
 	}
 
 #ifdef BUS_8080
+#ifndef FRONTPANEL
+	cpu_bus &= ~CPU_M1;
+#endif
 	cpu_bus |= CPU_WO | CPU_MEMR;
 #endif
 
@@ -118,7 +149,8 @@ static inline BYTE memrdr(WORD addr)
 		fp_led_data = data;
 		fp_sampleData();
 		wait_step();
-	}
+	} else
+		cpu_bus &= ~CPU_M1;
 #endif
 
 	return data;

diff --git a/cpmsim/srcsim/Makefile b/cpmsim/srcsim/Makefile
@@ -82,8 +82,8 @@ INSTALL_DATA = $(INSTALL) -m 644
 
 # core system source files for the CPU simulation
 CORE_SRCS = sim8080.c simcore.c simdis.c simfun.c simglb.c simice.c simint.c \
-	simmain.c simutil.c simz80.c simz80-cb.c simz80-dd.c simz80-ddcb.c \
-	simz80-ed.c simz80-fd.c simz80-fdcb.c
+	simmain.c simz80.c simz80-cb.c simz80-dd.c simz80-ddcb.c simz80-ed.c \
+	simz80-fd.c simz80-fdcb.c
 SRCS = $(CORE_SRCS) $(MACHINE_SRCS) $(IO_SRCS)
 OBJS = $(SRCS:.c=.o)
 DEPS = $(SRCS:.c=.d)

diff --git a/cpmsim/srcsim/sim.h b/cpmsim/srcsim/sim.h
@@ -15,14 +15,17 @@
 #define CPU_SPEED 0	/* default CPU speed 0=unlimited */
 /*#define ALT_I8080*/	/* use alt. 8080 sim. primarily optimized for size */
 /*#define ALT_Z80*/	/* use alt. Z80 sim. primarily optimized for size */
-#define UNDOC_INST	/* compile undocumented instructions */
+#define UNDOC_INST	/* compile undocumented instrs. (required by ALT_*) */
+#ifndef EXCLUDE_Z80
 #define FAST_BLOCK	/* much faster but not accurate Z80 block instr. */
+#endif
 
 /*#define WANT_ICE*/	/* attach ICE to machine */
 #ifdef WANT_ICE
 /*#define WANT_TIM*/	/* don't count t-states */
 /*#define HISIZE  1000*//* no history */
-/*#define SBSIZE  10*/	/* no breakpoints */
+/*#define SBSIZE  10*/	/* no software breakpoints */
+/*#define WANT_HB*/	/* no hardware breakpoint */
 #endif
 
 #define HAS_DISKS	/* uses disk images */

diff --git a/cpmsim/srcsim/simmem.h b/cpmsim/srcsim/simmem.h
@@ -28,13 +28,21 @@
  * 03-FEB-2017 added ROM initialization
  * 09-APR-2018 modified MMU write protect port as used by Alan Cox for FUZIX
  * 04-NOV-2019 add functions for direct memory access
+ * 14-DEC-2024 added hardware breakpoint support
  */
 
 #ifndef SIMMEM_INC
 #define SIMMEM_INC
 
 #include "sim.h"
 #include "simdefs.h"
+#ifdef WANT_ICE
+#include "simice.h"
+#endif
+
+#ifdef BUS_8080
+#include "simglb.h"
+#endif
 
 #define MAXSEG 16		/* max. number of memory banks */
 #define SEGSIZ 49152		/* default size of one bank = 48 KBytes */
@@ -49,6 +57,15 @@ extern int selbnk, maxbnk, segsize, wp_common;
  */
 static inline void memwrt(WORD addr, BYTE data)
 {
+#ifdef BUS_8080
+	cpu_bus &= ~(CPU_M1 | CPU_WO | CPU_MEMR);
+#endif
+
+#ifdef WANT_HB
+	if (hb_flag && hb_addr == addr && (hb_mode & HB_WRITE))
+		hb_trig = HB_WRITE;
+#endif
+
 	if ((addr >= segsize) && (wp_common != 0)) {
 		wp_common |= 0x80;
 #ifndef EXCLUDE_Z80
@@ -70,13 +87,34 @@ static inline void memwrt(WORD addr, BYTE data)
 
 static inline BYTE memrdr(WORD addr)
 {
+	register BYTE data;
+
+#ifdef WANT_HB
+	if (hb_flag && hb_addr == addr) {
+		if (cpu_bus & CPU_M1) {
+			if (hb_mode & HB_EXEC)
+				hb_trig = HB_EXEC;
+		} else {
+			if (hb_mode & HB_READ)
+				hb_trig = HB_READ;
+		}
+	}
+#endif
+
 	if (selbnk == 0)
-		return *(memory[0] + addr);
+		data = *(memory[0] + addr);
 
 	if (addr >= segsize)
-		return *(memory[0] + addr);
+		data = *(memory[0] + addr);
 	else
-		return *(memory[selbnk] + addr);
+		data = *(memory[selbnk] + addr);
+
+#ifdef BUS_8080
+	cpu_bus &= ~CPU_M1;
+	cpu_bus |= CPU_WO | CPU_MEMR;
+#endif
+
+	return data;
 }
 
 /*

diff --git a/cromemcosim/srcsim/Makefile b/cromemcosim/srcsim/Makefile
@@ -131,8 +131,8 @@ INSTALL_DATA = $(INSTALL) -m 644
 
 # core system source files for the CPU simulation
 CORE_SRCS = sim8080.c simcore.c simdis.c simfun.c simglb.c simice.c simint.c \
-	simmain.c simutil.c simz80.c simz80-cb.c simz80-dd.c simz80-ddcb.c \
-	simz80-ed.c simz80-fd.c simz80-fdcb.c
+	simmain.c simz80.c simz80-cb.c simz80-dd.c simz80-ddcb.c simz80-ed.c \
+	simz80-fd.c simz80-fdcb.c
 SRCS = $(CORE_SRCS) $(MACHINE_SRCS) $(IO_SRCS)
 XXSRCS = $(FP_SRCS)
 OBJS = $(SRCS:.c=.o) $(XXSRCS:.cpp=.o)

diff --git a/cromemcosim/srcsim/sim.h b/cromemcosim/srcsim/sim.h
@@ -26,6 +26,7 @@
  * 14-JUL-2022 added generic AT modem and HAL
  * 09-MAY-2024 added more defines for conditional compiling components
  * 15-MAY-2024 make disk manager standard
+ * 14-DEC-2024 added hardware breakpoint support
  */
 
 #ifndef SIM_INC
@@ -39,14 +40,17 @@
 #define CPU_SPEED 4	/* default CPU speed */
 /*#define ALT_I8080*/	/* use alt. 8080 sim. primarily optimized for size */
 /*#define ALT_Z80*/	/* use alt. Z80 sim. primarily optimized for size */
-#define UNDOC_INST	/* compile undocumented instructions */
+#define UNDOC_INST	/* compile undocumented instrs. (required by ALT_*) */
+#ifndef EXCLUDE_Z80
 /*#define FAST_BLOCK*/	/* much faster but not accurate Z80 block instr. */
+#endif
 
 /*#define WANT_ICE*/	/* attach ICE to headless machine */
 #ifdef WANT_ICE
 /*#define WANT_TIM*/	/* don't count t-states */
 /*#define HISIZE  1000*//* no history */
-/*#define SBSIZE  10*/	/* no breakpoints */
+/*#define SBSIZE  10*/	/* no software breakpoints */
+/*#define WANT_HB*/	/* no hardware breakpoint */
 #endif
 
 #define HAS_DAZZLER	/* has simulated I/O for Cromemco Dazzler */

diff --git a/cromemcosim/srcsim/simcfg.c b/cromemcosim/srcsim/simcfg.c
@@ -27,7 +27,6 @@
 #include "simdefs.h"
 #include "simglb.h"
 #include "simmem.h"
-#include "simutil.h"
 #include "simcfg.h"
 
 #include "log.h"
@@ -71,7 +70,7 @@ void config(void)
 				continue;
 			}
 			if (!strcmp(t1, "fp_port")) {
-				fp_port = (BYTE) exatoi(t2);
+				fp_port = (BYTE) strtol(t2, NULL, 16);
 			} else if (!strcmp(t1, "fp_fps")) {
 #ifdef FRONTPANEL
 				fp_fps = (float) atoi(t2);