AXI Memory Over TL Serial Link

[abejgonzalez]

This setup matches closely with the current Berkeley bringup setup where the AXI memory interface resides over the serial link and is in a different clock domain.

• Adds new connectHarnessMultiClockAXIRAM and MultiClockSerialAXIRAM functions/modules that have AXI memory interface over TL serial link
• Defaults to using async crossing
• Expands SerialTLParams to keep track of AXI clock freq. (used in IO/HarnessBinder to specify clock source and correctly give SimDRAM frequency)
• Add config. fragments to change AXI clock freq. and modify BlockDevice attach locations

[jerryz123]

Niceeeee.
Since this should be strictly better than the Harness TLRAM, can we replace the chipyard examples (if any) that use the TLRAM with this implementation?

[abejgonzalez]

While this is strictly better than those examples... there is one caveat... passing an extra clock/reset wire from the SoC over to this harness module. This is needed for FireSim to work (since all clocks need to come from the SoC... unless you want the clock bridge to be wired weirdly to both the harness and the SoC - though both reside in the "target" domain)

[colinschmidt]

Seems pretty reasonable to me.

[colinschmidt]

Everything looks good except for the reset change at the end.

[colinschmidt]

Isn't this getting the frequency from what the serial link masters rather than what masters the serial link?

[abejgonzalez]

Oh yea this comment is off. The serial link masters the FBUS and is slave to the MBUS. The code is still fine though.

[jerryz123]

LGTM