Merge remote-tracking branch 'origin/master' into tile-reset-async

ucb-bar · Mar 12, 2021 · 282ca2e · 282ca2e
2 parents 592fa20 + eda0018
commit 282ca2e
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Showing 4 changed files with 4 additions and 4 deletions.
diff --git a/CHIPYARD.hash b/CHIPYARD.hash
@@ -1 +1 @@
-c5cb8f13294f873da0dd62b25a4b8731b5337efb
+c5cb8f13294f873da0dd62b25a4b8731b5337efb
diff --git a/src/main/resources/testchipip/csrc/SimDRAM.cc b/src/main/resources/testchipip/csrc/SimDRAM.cc
@@ -15,7 +15,7 @@ extern "C" void *memory_init(
         long long int word_size,
         long long int line_size,
         long long int id_bits,
-	long long int clock_hz
+        long long int clock_hz
 			     )
 {
     mm_t *mm;

diff --git a/src/main/resources/testchipip/vsrc/SimDRAM.v b/src/main/resources/testchipip/vsrc/SimDRAM.v
@@ -51,7 +51,7 @@ module SimDRAM #(
               MEM_SIZE = 1000 * 1000 * 1000,
               LINE_SIZE = 64,
               WORD_SIZE = DATA_BITS/8,
-	      CLOCK_HZ = 100000,
+              CLOCK_HZ = 100000,
               STRB_BITS=DATA_BITS/8)(
   input                  clock,
   input                  reset,

diff --git a/src/main/scala/ClockUtil.scala b/src/main/scala/ClockUtil.scala
@@ -90,7 +90,7 @@ class ClockMutexMux(val n: Int, depth: Int, genClockGate: () => ClockGate) exten
 
     val andClocks = io.clocksIn.map(x => ClockSignalNor2(ClockInverter(x), io.resetAsync))
 
-    val syncs  = andClocks.map { c => withClockAndReset(c, io.resetAsync) { Module(new AsyncResetSynchronizerShiftReg(1, 3, 0)) } }
+    val syncs  = andClocks.map { c => withClockAndReset(c, io.resetAsync) { Module(new AsyncResetSynchronizerShiftReg(1, sync = depth, init = 0)) } }
     val gaters = andClocks.map { c =>
         val g = Module(genClockGate())
         g.io.in := c
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		c5cb8f13294f873da0dd62b25a4b8731b5337efb
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